an error on multi-source, but I can't understand...

[Neil]

Hi, All,
I encounter an error when synthesis with ISE 7.1i webpack.

-- ************************************************ --
-- part of the code as follow: --

-- process a --
a: process(clk,reset)
begin
if reset='1' then
LoadA<='0';
wr<='0';
elsif clk'event and clk='1' then
if wr='1' and TxBusy='0' then
... ...
-- more code here --
... ...
end if;
end if;
end process;

-- process b --
b: process(clk,reset)
begin
if reset='1' then
ReadA<='0';
rdReq<='0';
elsif clk'event and clk='1' then
if RxData=x"01" then
wr<='1';
... ...
... ...
elsif RxData=x"02" then
wr<='0';
... ...
... ...
end if;
end if;
end process;

-- ************************************************ --

the error is:"Xst:528 - Multi-source in Unit <...> on signal <wr>".
but I don't find any multi-source for it, and these two processes are
only triggered by clk or reset.

And if I move the assignment "wr <= '0';" from process a to process b,
and also place it under "if reset = '1'" clause, the error disappears.
What's the difference between them? I can't understand... Can anyone
help me explain it? Thank you!

Regards!
-- Neil

 

[Neil]

Hi, Ralf
I'm a beginner in VHDL, and I can't understand your explanation well...

Even each process will generate a signal driver for the signal
separately, there is also assert function / assert signal to determin
the value of the signal at that time. So why does it mean is there two
wire in real world? It always has only one proper value at a time...

And if "wr <= '0';" is placed in the reset-clause in the process b, how
many wires are there? one or two?
And how to know how many wires will be gotten for a signal in the real
world? Thank you!

Regards!
-- Neil

 

[ajahn]

Hi Neil,
try to see every process and every concurrent assignment in your block
as a black box. Signals are the wires between them. If you assign
values to signals in such a box, you produce a driver to a wire
(signal). It does not matter, that you only assign a value during
reset, once you write to the signal, the driver is there. If you assign
a value only during reset, you actually produce a flipflop that is
reset to some value and then drives this value all the time. This is
then optimized in a synthesis tool so that the flipflop becomes a
constant driver.
The thing with hdl's is you have to try to think hardware not just
"program" something...

I hope that helps you a bit..
Andreas

 

[Neo]

in short remove the statement "wr<='0'; " from the process-a and put it
in process-b

 

[ajahn]

Ralf, I don't think, process a will be a wire. It will rather be a FF
with output looped back to its input and an async reset. If you
simulate it, the behavior would be to have 'U' assigned to it upon
simulator initialization and '0' during and all the time after reset. A
wire would be '0' all the time... like a concurrent wr <= '0'; .
Of course synthesis tools will optimize this to be a wire....

Cheers,
Andreas.

 

[Andy Peters]

Neil wrote:

Hi, All,
I encounter an error when synthesis with ISE 7.1i webpack.

-- ************************************************ --
-- part of the code as follow: --

-- process a --
a: process(clk,reset)
begin
if reset='1' then
LoadA<='0';
wr<='0';

wr is assigned here ...

elsif clk'event and clk='1' then
if wr='1' and TxBusy='0' then
... ...
-- more code here --
... ...
end if;
end if;
end process;

-- process b --
b: process(clk,reset)
begin
if reset='1' then
ReadA<='0';
rdReq<='0';
elsif clk'event and clk='1' then
if RxData=x"01" then
wr<='1';

... and here ...

... ...
... ...
elsif RxData=x"02" then
wr<='0';
... ...
... ...
end if;
end if;
end process;

Simple reason for the synthesis complaint: Your problem is that you're
assigning the same signal in two processes. If you want to generate
real hardware, you can't do that.

-a

 

[Neil]

Now, I almost get it.
Thank you, All