Among the variable types in Verilog, which are signed

[parag_paul@hotmail.com]

hi All
Are Integers , realtime, time etc all signed by default,
Since the LRM says that signed be used only against reg, what about
the other variable types in Verilog.

Integers I have seen them to be signed by default, but what about real
data type
-Parag

 

parag_paul@hotmail.com wrote:

hi All
Are Integers , realtime, time etc all signed by default,
Since the LRM says that signed be used only against reg, what about
the other variable types in Verilog.

time is unsigned. It is just an unsigned 64-bit vector, but with the
implied intent to hold a simulation time.

realtime is a synonym for real, but with the implied intent to hold a
simulation time.

Integers I have seen them to be signed by default, but what about real
data type

Reals are floating point values, which are inherently signed. An
unsigned floating point type would be a little strange.

 

[parag_paul@hotmail.com]

Why will it be strange to see an unsigned real number.
That can double the mantissa value.isnt it ?

 

parag_paul@hotmail.com wrote:

Why will it be strange to see an unsigned real number.
That can double the mantissa value.isnt it ?

It could add 1 bit of precision to the mantissa value.

Problem domains that call for non-integer values generally call for
negative ones as well. So uses for unsigned reals would be limited.
Also, you would have to define the results of operations that would
normally come out negative, producing a strange number system. With
integers, it is well-understood modulo arithmetic.