AMIS C5 process

[horridnoodle@hotmail.com]

I am using the AMIS C5 process, and the Assuara rules for the drc lvs
and rcx. I am using poly to poly capacitors in my layout which are the
ones that were provided by Mosis as the AMIS device_examples. These
caps pass the drc just fine. However, from what I have seen there is no
corrisponding symbol in schematic for these poly to poly caps so the
LVS will not pass, and just gives a component mismatch. The layout
component is cap_pp. Has anyone else encountered this problem. If so,
how did they get around it.

Thanks

 

[Ekne]

Hi
So the LVS extracts the cap but you don't have a symbol for them in the
schematic so it will give a mismatch.
If you use ignoreCell("cap_pp") you will "filter" them out from the
layout side and the LVS should match.
I assume you have bypassed the stop on "unbound devices", i.e. continue
on error.
If not, the what is the contents on your .snn and .lnn ? Use vldboSpice
to get them in spice format.

But then is this what you want, ignore the layout side ?
If you want them nad have a 1 to 1 match you will need to have them on the
schematic side too.
It's easy to do a "local" symbol and instanciate it on the schematic as
cap_pp with the correct CDF's setup for
LVS purpose but since it's extracted as cap_pp the reference to the
correct symbol should be in the kit files.
Look in your extract.rul file what component the "cap_pp" refer to and
also take a look in the netlists files using
vldbToSpice command. Assuming that it's actually extracting this as cap_pp
i.e. is in your .lnn netlist.

Can't give you more help that this, since I don't have the files to check.
But looking at the netlists Assura creates from
schematic and layout will give you a hint on what it extracts.

By the way, DRC don't care about components, just check rules so anything
that follows the rules will pass ;-)

//BEE

<horridnoodle@hotmail.com> wrote in message
news:1144852774.219625.66870@i40g2000cwc.googlegroups.com...

I am using the AMIS C5 process, and the Assuara rules for the drc lvs
and rcx. I am using poly to poly capacitors in my layout which are the
ones that were provided by Mosis as the AMIS device_examples. These
caps pass the drc just fine. However, from what I have seen there is no
corrisponding symbol in schematic for these poly to poly caps so the
LVS will not pass, and just gives a component mismatch. The layout
component is cap_pp. Has anyone else encountered this problem. If so,
how did they get around it.

Thanks

 

[horridnoodle@hotmail.com]

Thanks very much.
I will give it a try.