Ambiguous type?

[Tuukka Toivonen]

Can anyone tell me why I'm getting the error messages
(and how to fix them):

ERROR: vhdl-bug.vhdl(25): Ambiguous type: ramy_arw_t or ramy_drw_t.
ERROR: vhdl-bug.vhdl(25): Illegal type conversion
ERROR: vhdl-bug.vhdl(26): Ambiguous type: ramy_arw_t or ramy_drw_t.
ERROR: vhdl-bug.vhdl(26): Illegal type conversion
ERROR: vhdl-bug.vhdl(29): VHDL Compiler exiting

from QuickHDL qvhcom v8.5_4.6f Feb 18 1997 SunOS 5.9 with the
following program:


use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity ME is end;

architecture RTL of ME is
subtype dim1 is std_ulogic_vector(16 downto 0);
type ramy_drw_t is array(0 to 199) of dim1;
type ramy_arw_t is array(0 to 199) of std_ulogic_vector(7 downto 0);

signal mb_y : std_ulogic_vector(4 downto 0);
signal mb_x : std_ulogic_vector(4 downto 0);
signal xfc_blk_y : std_ulogic;
signal xfc_blk_x : std_ulogic;
signal xfc_rd_y : std_ulogic_vector(3 downto 0);
signal xfc_rd_x : std_ulogic_vector(3 downto 0);
begin
process is
variable fby: unsigned(8 downto 0);
variable fbx: unsigned(8 downto 0);
begin
fby := unsigned(mb_y & xfc_blk_y & xfc_rd_y(2 downto 0)); -- line 25
fbx := unsigned(mb_x & xfc_blk_x & xfc_rd_x(2 downto 0)); -- line 26
wait;
end process;
end;

 

[Mike Treseler]

Tuukka Toivonen wrote

Can anyone tell me why I'm getting the error messages

Because concatenation works with any 1-D array
and a slice of ramy_drw_t is indistinguishable
from a slice of ramy_arw_t.

I assume you plan to use these types elsewhere,
but even though they aren't used in your example,
they are still in play when evaluating the right
hand side of your concatenation.

(and how to fix them)

The easy way is to comment out the unused types.

Another way is to reduce the number of types in play
like this:


use STD.TEXTIO.all;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity ME is end;

architecture RTL of ME is
subtype dim1 is unsigned(16 downto 0);
subtype dim2 is unsigned(7 downto 0);
type ramy_drw_t is array(0 to 199) of dim1;
type ramy_arw_t is array(0 to 199) of dim2;

signal mb_y : unsigned(4 downto 0);
signal mb_x : unsigned(4 downto 0);
signal xfc_blk_y : std_ulogic;
signal xfc_blk_x : std_ulogic;
signal xfc_rd_y : unsigned(3 downto 0);
signal xfc_rd_x : unsigned(3 downto 0);
begin
process is
variable fby: unsigned(8 downto 0);
variable fbx: unsigned(8 downto 0);
begin
fby := mb_y & xfc_blk_y & xfc_rd_y(2 downto 0); -- line 25
fbx := mb_x & xfc_blk_x & xfc_rd_x(2 downto 0); -- line 26
wait;
end process;
end;

-- Mike Treseler

 

[Stefan Frank]

On 05/03/2004 02:36 PM, Tuukka Toivonen wrote:

Even though I still don't understand what's happening,
I fixed the problem as your example hinted, by changing
the std_ulogic_vectors into unsigned and concatenating
only after that. Now it works, I just don't have idea
what is different now than before.

Hello Tuukka,

the following thread might help you:

<http://groups.google.com/groups?q=Weird,VHDL'isms>

Bye,
Stefan

 

[Tuukka Toivonen]

In article <865ab498.0404301531.6f3bb45c@posting.google.com>, Mike Treseler wrote:

Tuukka Toivonen wrote
Can anyone tell me why I'm getting the error messages
Because concatenation works with any 1-D array
and a slice of ramy_drw_t is indistinguishable
from a slice of ramy_arw_t.

Yes, but since all of the types I am concatenating
are either std_ulogic or std_ulogic_vector, and
I expect the result to be also std_ulogic_vector,
I don't understand what _either_ of those types
have to do here.

Even though I still don't understand what's happening,
I fixed the problem as your example hinted, by changing
the std_ulogic_vectors into unsigned and concatenating
only after that. Now it works, I just don't have idea
what is different now than before.

(ie. now I have
fby := unsigned(mb_y) & xfc_blk_y & unsigned(xfc_rd_y(2 downto 0));
fbx := unsigned(mb_x) & xfc_blk_x & unsigned(xfc_rd_x(2 downto 0));
)