Ambigous operator '&'

[Mohammed A khader]

HI all,

While compiling my design in Quartus II 4.2 , I got following errors.
The piece of code is given below....

Error: VHDL error at Ctrl_Ram.Vhd(66): can't determine definition of
operator ""&"" -- found 2 possible definitions
Error: Verilog HDL or VHDL error at Ctrl_Ram.Vhd(66): Unconverted
VHDL-1402: ambiguous type: 'Regfile' or 'SIGNED'
Error: VHDL Type Conversion error at Ctrl_Ram.Vhd(66): can't determine
type of object or expression near text or symbol "UNSIGNED"
Error: Ignored construct Ctrl_Ram_Arch at Ctrl_Ram.Vhd(42) because of
previous errors


-- These subtypes are in a package....

subtype WORD is signed(15 downto 0);
subtype DWORD is unsigned(31 downto 0);


-- In the Architecture declaration part I am defining follwing
signals..


type Regfile is array (natural range<&gt of WORD;
signal Regfile_Ctrl_High : Regfile(0 to 15); -- High Bank Registe File
signal Regfile_Ctrl_Low : Regfile(0 to 15); -- Low Bank Register File

signal data_out_high : WORD;
signal data_out_low : WORD;


-- And these are the concurrent statements in Architecture body...

-- Regfile Read Assignments
data_out_low <= Regfile_Ctrl_Low(TO_INTEGER(Addrs_In));
data_out_high <= Regfile_Ctrl_High(TO_INTEGER(Addrs_In));

-- Concatenation of Low and High to form 32 Control Word
Data32_Out <= unsigned(data_out_high & data_out_low); -- ERROR IS IN
THIS LINE...

Whats wrong with the last statment. I expect '&' operator to
concatenate the two signals. What could be the other meaning of '&'
operator. I think I am doing a silly mistake some where . Please help
me in resolving this..

Thanks.
-- Mohammed A Khader.

 

[Mohammed A khader]

Thanks ! It Worked .. But both are logically equal. What was my
mistake ?

 

[Mohammed A khader]

HI Mike,

Using & on your own array types without writing an overload for "&".

my signals 'data_out_high' and 'data_out_low' are subtype of signed.
Hence I expect that sysnthesis tool does'nt consider it as a new type.