Always

[Luiz Gustavo]

What's the difference and put or not, "begin" and "end", in the
"always"?

PS.: Sorry for english.

 

[Andy Peters]

Luiz Gustavo wrote:

What's the difference and put or not, "begin" and "end", in the
"always"?

PS.: Sorry for english.

If you have exactly one statement in your always block, you can omit
the begin and end.

always @(posedge clk)
q <= d;

If your always block needs more than one statement, then it needs a
begin and end:

always @(posedge clk) begin
q <= d;
a <= b;
end

If you like named blocks (and I do), then the begin/end is needed:

always @(posedge clk) begin : dflop
q <= d;
end // dflop

The rules are the same for begin/end with always as they are for any
statement where begins/ends may be necessary, for instance if blocks,
etc.
-a

 

[Luiz Gustavo]

First off al thank you very much...

In this case:

always @(negedge clk)
if (ld)
begin
mem_in [mem_adr_in] <= sri;
mem_adr_in <= mem_adr_in + 1'b1;
end

The struct of "if" is consider as one statement?




Andy Peters escreveu:

Luiz Gustavo wrote:
What's the difference and put or not, "begin" and "end", in the
"always"?

PS.: Sorry for english.

If you have exactly one statement in your always block, you can omit
the begin and end.

always @(posedge clk)
q <= d;

If your always block needs more than one statement, then it needs a
begin and end:

always @(posedge clk) begin
q <= d;
a <= b;
end

If you like named blocks (and I do), then the begin/end is needed:

always @(posedge clk) begin : dflop
q <= d;
end // dflop

The rules are the same for begin/end with always as they are for any
statement where begins/ends may be necessary, for instance if blocks,
etc.
-a

 

[Andy Peters]

Luiz Gustavo wrote:

Andy Peters escreveu:

Luiz Gustavo wrote:
What's the difference and put or not, "begin" and "end", in the
"always"?

PS.: Sorry for english.

If you have exactly one statement in your always block, you can omit
the begin and end.

always @(posedge clk)
q <= d;

If your always block needs more than one statement, then it needs a
begin and end:

always @(posedge clk) begin
q <= d;
a <= b;
end

If you like named blocks (and I do), then the begin/end is needed:

always @(posedge clk) begin : dflop
q <= d;
end // dflop

The rules are the same for begin/end with always as they are for any
statement where begins/ends may be necessary, for instance if blocks,
etc.
-a

First off al thank you very much...

You're welcome. Please don't top-post.

In this case:

always @(negedge clk)
if (ld)
begin
mem_in [mem_adr_in] <= sri;
mem_adr_in <= mem_adr_in + 1'b1;
end

The struct of "if" is consider as one statement?

Yes, and this is explained in any of the several available.Verilog
books.

0a