always vs forever

[sajid]

I am confused about what is the difference in always and forever. Any
help please?

 

sajid wrote:

I am confused about what is the difference in always and forever. Any
help please?

The behavior of 'always' is equivalent to 'initial forever'. In other
words, if you have

always
<statement>

This is equivalent in behavior to

initial
forever
<statement>

However, synthesis tools will generally treat them differently. They
assume that an 'always' is intended to represent real hardware while an
'initial' is not. This is just a heuristic based on the way they are
generally used.

 

[Alexsh]

sajid, your are right.
These two statements are very similar. For simulation they can do the
same. Both initial-forever and always start at time 0 and run till the
simulation ends.
The main difference is that initial statement describes "flow" of
commands. If these commands are to be executed step by step, we could
write

initial begin
command1...;
command2...;
command3...;
end

One of these commands could be "forever", but in begin-end block it
will be never finished, however you can write
initial fork
begin
forever ....;
end
begin
forever ....;
end
command...;
join

initial block is not synthesizable. It describes flow but not hardware.
To describe registers use always blocks only.