always @* vs. always @(*)

[Jonathan Bromley]

On Thu, 08 Nov 2007 02:14:20 -0800,
GilGr <gil.greenstein@gmail.com> wrote:

I was told there is a difference between the 2, "always @*" and
"always @(*)", and I'm trying to understand, since it doesn't sound
right to me.
I'm using synopsys VCS, can it have a problem like this?

They are two alternative forms of exactly the same thing.
The @(*) form looks very similar to attribute syntax
(*attribute...*) and so it's probably best to avoid it,
so that you have absolutely no risk of falling foul
of any bizarre ambiguities. But I've used it many
times without trouble.

I can't see any objection to @*, though.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[GilGr]

I was told there is a difference between the 2, "always @*" and
"always @(*)", and I'm trying to understand, since it doesn't sound
right to me.
I'm using synopsys VCS, can it have a problem like this?

thanks, Gil

 

[gabor]

On Nov 8, 1:23 pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:

On Thu, 08 Nov 2007 02:14:20 -0800,

GilGr <gil.greenst...@gmail.com> wrote:
I was told there is a difference between the 2, "always @*" and
"always @(*)", and I'm trying to understand, since it doesn't sound
right to me.
I'm using synopsys VCS, can it have a problem like this?

They are two alternative forms of exactly the same thing.
The @(*) form looks very similar to attribute syntax
(*attribute...*) and so it's probably best to avoid it,
so that you have absolutely no risk of falling foul
of any bizarre ambiguities. But I've used it many
times without trouble.

I can't see any objection to @*, though.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

I've seen editors, notably the Xilinx ISE editor, that
will color the (*) grey. Synthesis works properly, but
apparently the editor had a simpler algorithm for finding
and coloring an attribute.

 

Jonathan,

What is the VHDL equivalent for this "always @(*)"?
I'm using VHDL and I've seen this a couple of times.

Thanks in advance,

Luc

On Thu, 08 Nov 2007 18:23:14 +0000, Jonathan Bromley
<jonathan.bromley@MYCOMPANY.com> wrote:

On Thu, 08 Nov 2007 02:14:20 -0800,
GilGr <gil.greenstein@gmail.com> wrote:

I was told there is a difference between the 2, "always @*" and
"always @(*)", and I'm trying to understand, since it doesn't sound
right to me.
I'm using synopsys VCS, can it have a problem like this?

They are two alternative forms of exactly the same thing.
The @(*) form looks very similar to attribute syntax
(*attribute...*) and so it's probably best to avoid it,
so that you have absolutely no risk of falling foul
of any bizarre ambiguities. But I've used it many
times without trouble.

I can't see any objection to @*, though.

 

[Jonathan Bromley]

On Thu, 15 Nov 2007 15:16:29 GMT, lb.edc@telenet.be wrote:

What is the VHDL equivalent for this "always @(*)"?

Sadly, there is none.

VHDL-200x enhancements will include "process(all)"
(I think that's the correct syntax) but I don't
know of any tools supporting it yet.
--
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.

 

[Mike Treseler]

Jonathan Bromley wrote:

On Thu, 15 Nov 2007 15:16:29 GMT, lb.edc@telenet.be wrote:
What is the VHDL equivalent for this "always @(*)"?

Sadly, there is none.

I like this workaround:
process(reset, clock)

Synthesis does a fine job wiring up
the D sides for me

-- Mike Treseler