always @ (posedge clk or negedge rstn)

[krby_xtrm]

i am a vhdl programmer, and i want to know what does:
always @ (posedge clk or negedge rstn) mean?
if (!rstn)
.. do something...
else if (condition)
.. do something.

is it synchonous with clk with assync reset?

 

[Naren]

Hi,
Its very similar to

process (clk, rstn)
begin
if (rstn = '0') then
.. do 1 ..
elsif (clk'event and clk='1') then
if (condition) then
.. do 2 ..
endif;
endif;
end process;

Thanks & Regards,
Naren.
Design Verification Engineer,
TooMuch Semiconductor Solutions Pvt. Ltd.
Bangalore.

krby_xtrm wrote:

i am a vhdl programmer, and i want to know what does:
always @ (posedge clk or negedge rstn) mean?
if (!rstn)
.. do something...
else if (condition)
.. do something.

is it synchonous with clk with assync reset?

 

Naren wrote:

Hi,
Its very similar to

process (clk, rstn)
begin
if (rstn = '0') then
.. do 1 ..
elsif (clk'event and clk='1') then
if (condition) then
.. do 2 ..
endif;
endif;
end process;

A VHDL regular might write it like this:

process (clk, rstn)
begin
if rstn = '0' then
.. do 1 ..
elsif rising_edge(clk) then
if condition then
.. do 2 ..
endif;
endif;
end process;

The parentheses aren't needed around an 'if' condition, and
rising_edge(clk) is much more obvious than clk'event and clk = '1'.

Regards,
Allan

 

[Mark McDougall]

allanherriman@hotmail.com wrote:

The parentheses aren't needed around an 'if' condition, and
rising_edge(clk) is much more obvious than clk'event and clk = '1'.

Heh, perhaps the OP has a software background?

I've been working on projects where I am editing Verilog, VHDL and C all
at the same time - and it's not uncommon to start writing C in the
middle of your VHDL/Verilog code and vice-versa! I'm forever going back
and deleting brackets around 'if' conditions in my VHDL too!

Regards,
Mark

 

yes.

always @ (posedge clk)
if (!rstn)
.. do something...
else if (condition)
.. do something.

will generate a synchronous reset. In older Synopsys, 2003--, this
could also lead to large unknown cones unless //priority rstn was used
or something similar. Newer versions -- I haven't been a synthesis
jockey for a while -- may be better.

P

 

[svtechie@gmail.com]

krby_xtrm wrote:

i am a vhdl programmer, and i want to know what does:
always @ (posedge clk or negedge rstn) mean?
if (!rstn)
.. do something...
else if (condition)
.. do something.

is it synchonous with clk with assync reset?

Yes.. you are absolutely right

- svtechie
www.svtechie.com