always (*) - Is it inefficient ?

[aman]

In verilog 2001 it is allowed to say always(*) and there is no need to
specify long sensitivity lists. Will the always block trigger on only
the signals which are read in that always block or will it trigger on
every input ?

 

[Ajeetha]

Yes, it will internally populate sensitivty list appropriately. BTW, if
you can, start using always_comb in SV - that's even better than this
always @(*). One of the main advantages of that is it can also prvent
any accidental multiple drivers!

HTH
Ajeetha, CVC
www.noveldv.com

 

[aman]

As far as I understood, always_comb is a keyword used in System
Verilog. Can I use always_comb in verilog 2001 ?

 

[Ajeetha]

Aman,
Yes it is in SV (SystemVerilog), not V2K.

Ajeetha, CVC

 

I am not sure what you mean by "every input". It will not trigger on
every input signal to the module where it appears. It will trigger on
every net or variable that is read by that always block.

And the syntax is @* or @(*), not always(*). It is not a part of the
always itself. It is an event control. When used on the statement
inside an always block, as it invariably is, the resulting syntax will
be always @* stmt, or always @(*) stmt.

 

[aman]

Thanks. That makes sense.