"always" construct in verilog?

[Lee]

Dear all,

If I want to construct a combination circuit, can I use "always"
construct?

I feel confused:
If I use "always", the left hand side of equation must be "reg"
type,right? This way, I introduced a register. That is not a
combinational circuit.Right?

What is wrong with this?How to understand it?

Thanks all the same,

Adrian

 

[ka]

On 8 Jun 2004 15:51:08 -0700, yxl4444@louisiana.edu (Lee) wrote:

Dear all,

If I want to construct a combination circuit, can I use "always"
construct?

I feel confused:
If I use "always", the left hand side of equation must be "reg"
type,right? This way, I introduced a register. That is not a
combinational circuit.Right?

What is wrong with this?How to understand it?

This is one of the most confusing features of Verilog. The problem is
that a register doesn't necessarily generate a storage element and the
requirement that a name has to be declared a register to be assigned
in an always block as opposed to a wire in a continuous assignment is
completely arbitrary. There is no difference between the two blocks:

wire a = b && c;

reg a;
always @(b or c)
a = b && c;

The only time when a register generates a "register" is when the
assignment needs storage. This happens when you use an edge based even
in the dependency list or incomplete assignment in the always blocks
(ie where some logic paths don't assign any values so the previous
value have to be remembered). The former usually generates a DFF and
the latter generates a latch.

 

[glen herrmannsfeldt]

Lee wrote:

If I want to construct a combination circuit, can I use "always"
construct?

I feel confused:

If I use "always", the left hand side of equation must be "reg"
type,right? This way, I introduced a register. That is not a
combinational circuit.Right?

What is wrong with this?How to understand it?

Continuous assignment to me is more obviously combinatorial.

The assignments in the always block happen when the always
condition is satisfied. They are not continuous, so there
must be something to hold the value between changes.

From the book I have, a tristate buffer is described:

module tristate(yin, oe, yout);
output yout;
input yin, oe;
reg yout;
always @(oe) begin
if(oe) yout = yin;
else yout = 1'bz;
end
endmodule

Whenever oe changes, the value of yout is changed
as necessary. I think, though, that this one is wrong.
It should have always @(oe or yin) so that yout follows
changes to yin when oe is high.

-- glen