always block...

[Element Blue]

Hi all,
I have a doubt.Is the 'always' block always executed upon
intialization ? (Like a VHDL process ) And do assignments in the initial
block cause events to be scheduled at t=0 ? (if the assignments are at
t=0).
Like :
module contrived (in,out)
input in;
output out;
reg a,b;
intial begin
a=0;b=1;
end
always @a
begin
out=a and in;
end
always @b
begin
out=b and in;
end
endmodule;

Do the initial a,b assignments cause events which will lead to execution
of the always blocks ??
If there was no @a or @b in the always sens.list,will the always block be
executed at t=0??
Thanks a lot.

 

[Steven Sharp]

Element Blue <supreet@wrongdomain.com> wrote in message news:<Pine.LNX.4.61.0411091650100.30926@phenix.rootshell.be>...

Hi all,
I have a doubt.Is the 'always' block always executed upon
intialization ? (Like a VHDL process )

Yes, it is executed, but probably not the way you mean. It will
execute until it reaches an event control or delay control, and
then it will stop to wait. If the always block has an event
control at the very start, then execution will stop there. Then
the body of the always block will not execute until the event
control is triggered so that the process continues executing.

So if you write an always block with an event control at the
start, the body will not be unconditionally executed at time
zero. It is not equivalent to a VHDL process with a sensitivity
list, which inserts a wait at the bottom of the process body.
Instead, Verilog inserts the wait exactly where you put it, at
the top. If you stick an event control at the bottom, then it
will wait there instead.

And do assignments in the initial
block cause events to be scheduled at t=0 ? (if the assignments are at
t=0).

Yes, they do, but this may occur before or after always blocks
are executed and start waiting at their event controls.

Like :
module contrived (in,out)
input in;
output out;
reg a,b;
intial begin
a=0;b=1;
end
always @a
begin
out=a and in;
end
always @b
begin
out=b and in;
end
endmodule;

Do the initial a,b assignments cause events which will lead to execution
of the always blocks ??

If the always blocks have started executing already and have started
waiting at the event controls, then it will. If the initial block
executes before the always blocks, then the events will have happened
before the always blocks start waiting on them. The order of this
execution is undefined in the language, so you can't count on it.

If there was no @a or @b in the always sens.list,will the always block be
executed at t=0??

The always blocks are always executed at t=0. The @a and @b make them
stop until the events occur. These are *not* VHDL sensitivity lists.
The keyword "always" works just like "initial forever" would, starting
up an infinite loop process. I don't know VHDL, but I assume that it
naturally runs each process once at startup and once each time its
sensitivity is triggered. So Verilog always blocks run infinitely
by default, and are stopped by event controls. VHDL blocks run once
by default, and are started each time by events on their sensitivity
list. The resulting behavior is almost the same, except at t=0, and
if there is no event control or sensitivity list. You can also view
VHDL as being the same as Verilog, with a sensitivity list treated as
an event control at the *bottom* of the loop (and a wait on an empty
sensitivity list hanging forever).

 

[Chris Briggs]

Element Blue <supreet@wrongdomain.com> wrote in message news:<Pine.LNX.4.61.0411091650100.30926@phenix.rootshell.be>...

Do the initial a,b assignments cause events which will lead to execution
of the always blocks ??

I believe the correct answer is maybe. At least in the Verilog-1995
spec, this was unspecified and so different simulators behave
differently. Some simulators (at least VCS) have a switch to force it
to trigger always blocks if their sensitivity list detects a change at
time 0. See also this thread:
http://groups.google.com/groups?hl=en&lr=&c2coff=1&threadm=bj3dl0%24ig4%241%40sun-news.laserlink.net&rnum=1&prev=/groups%3Fhl%3Den%26lr%3D%26c2coff%3D1%26selm%3Dbj3dl0%2524ig4%25241%2540sun-news.laserlink.net

If there was no @a or @b in the always sens.list,will the always block be
executed at t=0??

There's another problem with that, at least in this example. Whether
or not they trigger at time 0, once they do trigger they'll
continuously retrigger in the same time slot because there's no delay
inside them. You'll create a zero-time loop and simulation time won't
advance.

always @a
begin
out=a and in;
end

Last note: in Verilog it's 'a & in' for bitwise-AND.

-cb

 

[Element Blue]

On Wed, 10 Nov 2004, Chris Briggs wrote:

Do the initial a,b assignments cause events which will lead to execution
of the always blocks ??

I believe the correct answer is maybe. At least in the Verilog-1995
spec, this was unspecified and so different simulators behave
differently. Some simulators (at least VCS) have a switch to force it
to trigger always blocks if their sensitivity list detects a change at
time 0. See also this thread:
http://groups.google.com/groups?hl=en&lr=&c2coff=1&threadm=bj3dl0%24ig4%241%40sun-news.laserlink.net&rnum=1&prev=/groups%3Fhl%3Den%26lr%3D%26c2coff%3D1%26selm%3Dbj3dl0%2524ig4%25241%2540sun-news.laserlink.net


If there was no @a or @b in the always sens.list,will the always block be
executed at t=0??

There's another problem with that, at least in this example. Whether
or not they trigger at time 0, once they do trigger they'll
continuously retrigger in the same time slot because there's no delay
inside them. You'll create a zero-time loop and simulation time won't
advance.

I meant to ask that,if indeed the always block executes at t=0,is
it due to event on sensitivity list (in case there was a @a) or is it
exeuted anyway (in case there is no @a) ? Say the always block had #5;
after the assignment,so that simulation could advance,so that isnt a
problem anymore.
As for my first question,I gather then that initial assignments
may or may not cause events depending on the simulator .

always @a
begin
out=a and in;
end

Last note: in Verilog it's 'a & in' for bitwise-AND.
Sorry about that. I ll be more careful next time.

Thanks.
-EB.

-cb