Always block with more than one clock signals

[Suman Nandan]

Hi,
In the following case, 'clk' and 'aclr2' can both (or combined)
act as the clock. Is it synthesisable?
If yes, what should be the hardware generated? Can anyone tell me what
is the
behavior of Design Compiler regarding this ?
Thanks,

module top (clk, aclr, aclr2, ena, data, q);
input clk, aclr, aclr2, ena, data;
output q;
reg q;

always @ (posedge clk or posedge aclr or posedge aclr2)
begin
if ((aclr) == 1)
q <= 1'b0;
else if (ena)
q <= data;
end
endmodule

 

[bullwfy]

Hi,

In my opinion, I dont think ur DC will map to any hardware. It might
give u an error or warning.

This is due to the library that u are using. If ur library do have a
flop that can support more than 1 clock edge. Then it can use that flop
and map it. But now from ur verilog code, it's seem like u are using 3
signal edges to trigger an output.

Plus, it is incomplete "if else". Are u trying to flop or latch it??

Correct me if I'm wrong and mayb other synthesis guru will give a
better explanation.

Hope it help

 

[morpheus]

what you're intending to do with your code is generate a flip flop with
two asynchonous resets. It may work but i would modify your code to the
following and then try
*********************************************************************
always @(posedge clk or posedge aclr or posedge aclr2)
begin
if((aclr) || (acl2))
begin
q<=1'b0;
end
else if(ena)
begin
q<=data;
end
else
begin
q <= q;
end
end
*************************************************************
What should happen is that the asynchronous reset will be generated
combinatorially.
I hope this works but I recommend that you look for better
implementations
Regards
MORPHEUS

 

[Suman Nandan]

morpheus wrote:

what you're intending to do with your code is generate a flip flop with
two asynchonous resets. It may work but i would modify your code to the
following and then try
*********************************************************************
always @(posedge clk or posedge aclr or posedge aclr2)
begin
if((aclr) || (acl2))
begin
q<=1'b0;
end
else if(ena)
begin
q<=data;
end
else
begin
q <= q;
end
end
*************************************************************
What should happen is that the asynchronous reset will be generated
combinatorially.
I hope this works but I recommend that you look for better
implementations
Regards
MORPHEUS

Thanks all,
actually I am intended to know what should be the behavior if two
signals can potentially act as a clock. In that case I think we should
just error out, rather than generating any harware. I want to know
your
views. In my library I dont have any FF/latch with more than one clock

input.
Thanks.

 

[Berty]

Generally speaking there is no such think as FF with two clock's.
You might have library that do something but it simple mean that
someone "play around" to somehow combine the two input to generate
one clock or use two FF and so on.

In the most generic way a FF can have one input of clock two input of
async reset and set and two input of sync set and reset, and maybe
clock enable which is basically a muxing back the output when the clock
is not enable.

By writing something which require two clock whether the synthesis will
manage to make something or not you take a huge risk that what you will
get is not what you want and it would be better to design it so you
have only one clock per FF and there is no "who knows what will
happen" scenario.

Have fun.

 

[Berty]

I'm not sure what Xilinx have in there DDR Output however I have a
strong feeling that even if it look to the user as one part with two
edge it is build from the 2 FF and mux like the "old way" (with
maybe extra latch).

Putting aside the FF base on two latch's one after the other and hence
you might say there is two edge possibility and taking only about the
general FF how do you build one FF with two clock edge ? From physical
point of view there is only one gate/clock.

Or maybe this is what you mean when you wrote notable that for the user
it look like two edge though inside it is build from two FF's (and
maybe a bit more) ?

Have fun.