alu implementation

[Manuel]

Hello,
I'm a student. I must realize a simple ALU with two register (16 bit)as
input and one register (16 bit)as output. The problem is the ALU in the
middle.
Input:
In_A(15:0)
In_B(15:0)
alu_op(3:0)
carry_in
Output:
alu_out(15:0)
z (flag of zero)
v (flag of overflow)
c (carry out)
n (signum of result)

alu_op has different configuration (e.g:0000 --> move a to output)
I have to put the input in vector of 17 bit (OK)
then i have to work on them and I have the result (in vector of 17
bit):in this way the first bit is carry out and the second is signum.
How can implement
1) a_decrement and
2) SBC (sub with carry)and
3) ADC (add with carry)?
4) how could use the bit for overflow?
I had a solution but i would compare it. I think:
1) a + "1111111111111111"
2) a-b+carry_in
3) a+b+carry_in or a+b+"100000000000000000"
4) maybe second bit?
I'm talking at logic level.
Thanks

Manuel


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[Ralf Hildebrandt]

Manuel wrote:

I'm a student. I must realize a simple ALU with two register (16 bit)as
input and one register (16 bit)as output. The problem is the ALU in the
middle.
Input:
In_A(15:0)
In_B(15:0)
alu_op(3:0)
carry_in
Output:
alu_out(15:0)
z (flag of zero)
v (flag of overflow)
c (carry out)
n (signum of result)

If you don't have any other signals, the input and output register are
"useless".

The ALU is just a combinatorical "bunch of gates".

alu_op has different configuration (e.g:0000 --> move a to output)

-> alu_op selects different results -> it is the selector of a mux

I have to put the input in vector of 17 bit (OK)

16 bits?

1) a_decrement and

res_dec<=in_A - 1;

Some type conversions are needed too - e.g.:

res_dec<=std_ulogic_vector(signed(in_A) - 1);

2) SBC (sub with carry)and

without the nessecary type conversions:

res_SBC<=in_A + NOT(in_B) + carry_in;

3) ADC (add with carry)?

again: without type conversons

res_ADD<=in_BA + in_B + carry_in;

4) how could use the bit for overflow?

* convert operands to signed
* use the RESIZE function provided in IEEE.numeric.std and resize the
operands to 17 bits
* compute a 17 bit result -> 17. bit is carry_out of addition ->
overflow

I had a solution but i would compare it. I think:
1) a + "1111111111111111"

o.k.

2) a-b+carry_in

Subtraction is

a + NOT(B) + 1

instead of the 1 the carry_in is taken

3) a+b+carry_in or a+b+"100000000000000000"

The 2nd option is wrong, because it is carry_IN! Furthermore carry_in
could be 0, too. Correct (in your style):

a+b+"00000000000000000C"
^here is the interesting point

4) maybe second bit?

Think about the idea, what does "overflow" mean! At addition it means,
that your sum is too large.



Ralf

 

[Manuellll]

My answer:

register are "useless".
Register are in project and have clock, enable and reset but it's not

interesting!

I have to put the input in vector of 17 bit (OK)
16 bits?
No 17 bits because it's useful to get the carry out bit!

so the input of the alu is '0'& A (that comes from register)

1) a_decrement and
res_dec<=in_A - 1;
Some type conversions are needed too - e.g.:
res_dec<=std_ulogic_vector(signed(in_A) - 1);

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[Manuelll]

continue...
No conversion

2) SBC without the nessecary type conversions:
res_SBC<=in_A + NOT(in_B) + carry_in;

Ok

3) ADC again: without type conversons
res_ADD<=in_BA + in_B + carry_in;
OK


4) how could use the bit for overflow?

* convert operands to signed
* use the RESIZE function provided in IEEE.numeric.std and resize
the
operands to 17 bits
* compute a 17 bit result -> 17. bit is carry_out of addition -
overflow
No Resize allowed!

Overflow could be get with two and (with three
input:notA,notB,ALU_result for the first
and A,B,notALU_result for the second)
and a OR(with the result of and as input and overflow as output)

Ralf

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