Alternative for "ifdef synthesis" directive??

[Viji]

I have simulation and synthesis model for Flip-Flop.
One way to do conditional compilation is to used " 'ifdef synthesis ".
If synthesis tool doesnt support the " 'ifdef synthesis "(ie the
"synthesis" macro is not defined by the synthesis tool by default)
what are the alternate option to tell synthesis tool to compile
synthesis Model and simulation tool to compile Simulation Code?

 

Viji wrote:

I have simulation and synthesis model for Flip-Flop.
One way to do conditional compilation is to used " 'ifdef synthesis ".
If synthesis tool doesnt support the " 'ifdef synthesis "(ie the
"synthesis" macro is not defined by the synthesis tool by default)
what are the alternate option to tell synthesis tool to compile
synthesis Model and simulation tool to compile Simulation Code?

The simulators have predefined macros for that. For example, NC-Sim has
the keyword "verilog":

`ifdef verilog
parameter PARAM = 4;
`endif

And pragmas are supported by synthesis tools. For example, Synplify has
the keyword "synthesis":

// synthesis translate_off
and2 (a, b, c[4]);
// synthesis translate_on

In the example above, the AND gate is not considered for synthesis.
The other tools have similar mechanisms. Check your tool manual.

Utku.

 

[Jim Wu]

Conditional generate should work. Your top level design can default to
synthesis. When you instantiate the top level design in your testbench,
you can then change the parameter to use the simulation model. e.g.

module tb;

top #(.SYNTHESIS (0)) (...)

endmodule

module top # (parameter SYNTHESIS = 1) (...)

generate
if (SYNTHESIS == 1)
ff_for_synthesis_here
else
ff_for_simulation_here
end generate

endmodule

HTH,
Jim
http://home.comcast.net/~jimwu88/tools/

Viji wrote:

I have simulation and synthesis model for Flip-Flop.
One way to do conditional compilation is to used " 'ifdef synthesis ".
If synthesis tool doesnt support the " 'ifdef synthesis "(ie the
"synthesis" macro is not defined by the synthesis tool by default)
what are the alternate option to tell synthesis tool to compile
synthesis Model and simulation tool to compile Simulation Code?