Altera Stratix synthesis error

[erojr]

I have transported a design from Altera APEX to STRATIX. The previous
design´s Lookup Tables (LUTs) that were in ¨lpm_rom¨ modules have been
transported to ¨altsynchram¨ modules. Now QuartusII3.0 sends an error
message:

Error: Groups cannot be assigned to nodes

When I locate the message´s origin, it points to the following file:

/appl/quartusII3.0/libraries/megafunctions/altsyncram.tdf

Here on the line #1501:

ram_block[0].portaaddr[] = address_a[];

The design itself was already simulated by Cadence(TM) on behavioral
level, with all lpm-s inside, without any error. The Synthesis tool
Synplify did not give error message either. Perhaps a bug in Quartus?

Any idea?

Thanks,

Janos Ero
CERN Div. EP

 

[Ben Twijnstra]

erojr wrote:

I have transported a design from Altera APEX to STRATIX. The previous
design´s Lookup Tables (LUTs) that were in ¨lpm_rom¨ modules have been
transported to ¨altsynchram¨ modules. Now QuartusII3.0 sends an error
message:

Error: Groups cannot be assigned to nodes

Doesn't sound like a familiar message. Can you post some code that
instantiates the altsyncram?

--
Ben

 

[erojr]

Ben Twijnstra wrote:

erojr wrote:

Error: Groups cannot be assigned to nodes



Doesn't sound like a familiar message. Can you post some code that
instantiates the altsyncram?

Thanks for your efforts. Yes, here you can see below.

Janos Ero

------------------------------------------------------------------------------

LIBRARY IEEE;
LIBRARY altera_mf;

USE IEEE.STD_LOGIC_1164.all;
USE IEEE.Numeric_std.all;
USE altera_mf.altera_mf_components.all;
USE work.dttf_pack.all;


ENTITY my_rom IS
GENERIC (
lpm_width : POSITIVE;
lpm_widthad : POSITIVE;
lpm_file : STRING
);
PORT (
address : IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
outclock : IN STD_LOGIC;
q : OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0)
);

END my_rom;

ARCHITECTURE rom_unit OF my_rom IS

COMPONENT altsyncram
GENERIC (
-- PORT A PARAMETERS
width_a : INTEGER := 1;
widthad_a : INTEGER := 1;
numwords_a : INTEGER := 1;
outdata_reg_a : STRING := "UNREGISTERED";
address_aclr_a : STRING := "NONE";
outdata_aclr_a : STRING := "NONE";
indata_aclr_a : STRING := "NONE";
wrcontrol_aclr_a : STRING := "NONE";
byteena_aclr_a : STRING := "NONE";
width_byteena_a : INTEGER := 1;

-- PORT B PARAMETERS
width_b : INTEGER := 1;
widthad_b : INTEGER := 1;
numwords_b : INTEGER := 1;
rdcontrol_reg_b : STRING := "CLOCK1";
address_reg_b : STRING := "CLOCK1";
outdata_reg_b : STRING := "UNREGISTERED";
outdata_aclr_b : STRING := "NONE";
rdcontrol_aclr_b : STRING := "NONE";
indata_reg_b : STRING := "CLOCK1";
wrcontrol_wraddress_reg_b : STRING := "CLOCK1";
byteena_reg_b : STRING := "CLOCK1";
indata_aclr_b : STRING := "NONE";
wrcontrol_aclr_b : STRING := "NONE";
address_aclr_b : STRING := "NONE";
byteena_aclr_b : STRING := "NONE";
width_byteena_b : INTEGER := 1;

-- GLOBAL PARAMETERS
operation_mode : STRING := "BIDIR_DUAL_PORT";
byte_size : INTEGER := 8;
read_during_write_mode_mixed_ports : STRING := "DONT_CARE";
ram_block_type : STRING := "AUTO";
init_file : STRING := "UNUSED";
init_file_layout : STRING := "UNUSED";
maximum_depth : INTEGER := 0;
intended_device_family : STRING := "Stratix";

lpm_hint : STRING := "UNUSED";
lpm_type : STRING := "altsyncram"
);

-- PORT DECLARATION
PORT (
-- INPUT PORT DECLARATION
wren_a : in std_logic := '0'; -- Port A write/read enable inp
wren_b : in std_logic := '0'; -- Port B write enable input
rden_b : in std_logic := 'Z'; -- Port B read enable input
data_a : in std_logic_vector(width_a - 1 downto 0) :=
(others => '0');
data_b : in std_logic_vector(width_b - 1 downto 0) :=
(others => '0');
address_a : in std_logic_vector(widthad_a - 1 downto 0) :=
(others => '0');
address_b : in std_logic_vector(widthad_b - 1 downto 0) :=
(others => '0');

clock0 : in std_logic := '1';
clock1 : in std_logic := '1';

clocken0 : in std_logic := '1';
clocken1 : in std_logic := '1';

aclr0 : in std_logic := '0';
aclr1 : in std_logic := '0';

byteena_a : in std_logic_vector( (width_byteena_a) - 1 downto 0)
:= (others => 'Z');
byteena_b : in std_logic_vector( (width_byteena_b) - 1 downto 0)
:= (others => 'Z');

-- OUTPUT PORT DECLARATION
q_a : out std_logic_vector(width_a - 1 downto 0);
q_b : out std_logic_vector(width_b - 1 downto 0)
);

END COMPONENT;

BEGIN

rom_comp : altsyncram
GENERIC MAP (
-- PORT A PARAMETERS
width_a => lpm_width,
widthad_a => lpm_widthad,
outdata_reg_a => "clock0",

-- GLOBAL PARAMETERS
operation_mode => "ROM",
ram_block_type => "AUTO",
init_file => lpm_file
)
PORT MAP (
-- INPUT PORT DECLARATION
address_a => address,
clock0 => outclock,

-- OUTPUT PORT DECLARATION
q_a => q
);

END rom_unit;