Altera SOPC SDRAM & CLK Input?

[Pino]

To all,

With the help of some of the newsgroup members (thanks alot) I
have been able to generate a sopc design with a user-defined master
with the Micron SDRAM controller using the library functions in SOPC
Builder. After I generated the system and download it to the FPGA on
a 1s10 Development Kit evaluation board, I realized that I was not
able to read/write to the memory. When I probed the evaluation board
which has a fan-out clock buffer, there was no clock feeding the
SDRAM. The fan-out buffer has 2 inputs, one coming from the on-board
50 MHz oscillator and the other coming from the FPGA. The second
output is what is tied to the SDRAM. This allows the FPGA to generate
a higher clock rate for the SDRAM. The problem is that when the
evaluation board is powered-up, I can actively see a clock signal at
the output of the FPGA. This is because on boot-up the Flash contains
the SAFE mode program running a webserver client. However, when I
download my program, the FPGA line seems to go low or into tri-state
and there is no clock generated. Can anyone help me resolve how to
enable this output line on the FPGA to retain it's clock?

Regards,
Pino

 

[Kenneth Land]

Pino,

Do you have your PLL external output clock tied to the SDRAM clock pin?
(plus all the other sdram pins?)
Did you start with an example like "Thrifty" etc.?

Ken


"Pino" <pinod01@sympatico.ca> wrote in message
news:b7ed9648.0407130601.6c8fae00@posting.google.com...

To all,

With the help of some of the newsgroup members (thanks alot) I
have been able to generate a sopc design with a user-defined master
with the Micron SDRAM controller using the library functions in SOPC
Builder. After I generated the system and download it to the FPGA on
a 1s10 Development Kit evaluation board, I realized that I was not
able to read/write to the memory. When I probed the evaluation board
which has a fan-out clock buffer, there was no clock feeding the
SDRAM. The fan-out buffer has 2 inputs, one coming from the on-board
50 MHz oscillator and the other coming from the FPGA. The second
output is what is tied to the SDRAM. This allows the FPGA to generate
a higher clock rate for the SDRAM. The problem is that when the
evaluation board is powered-up, I can actively see a clock signal at
the output of the FPGA. This is because on boot-up the Flash contains
the SAFE mode program running a webserver client. However, when I
download my program, the FPGA line seems to go low or into tri-state
and there is no clock generated. Can anyone help me resolve how to
enable this output line on the FPGA to retain it's clock?

Regards,
Pino

 

[Jesse Kempa]

"Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message news:<10f8r37ibfl3u8d@news.supernews.com>...

Pino,

Do you have your PLL external output clock tied to the SDRAM clock pin?
(plus all the other sdram pins?)
Did you start with an example like "Thrifty" etc.?

Ken

Ken is absolutely right about the PLL feeding the SDRAM clock being
necessary. One note, though: please take a look at an example design
specific to the board you're using (1s10). The reason I say this is
that the clock networks on our Nios/Cyclone boards (one PLL for Nios,
fed back into a second to drive SDRAM) are slightly different than the
Stratix boards (only one PLL required for both an on-FPGA and external
SDRAM clock).

Also note: be sure to phase shift the external clock to SDRAM. If you
open up the example designs and take a look at the PLL you'll see what
I mean. This will compensate for board trace delay and should be
adjusted if you build your own board which, obviously, will have its
own delay.

Jesse Kempa
Altera Corp.
jkempa at altera dot com

 

[Pino]

kempaj@yahoo.com (Jesse Kempa) wrote in message news:<95776079.0407140807.7cf919d1@posting.google.com>...

"Kenneth Land" <kland_not_this@neuralog_not_this.com> wrote in message news:<10f8r37ibfl3u8d@news.supernews.com>...
Pino,

Do you have your PLL external output clock tied to the SDRAM clock pin?
(plus all the other sdram pins?)
Did you start with an example like "Thrifty" etc.?

Ken


Ken is absolutely right about the PLL feeding the SDRAM clock being
necessary. One note, though: please take a look at an example design
specific to the board you're using (1s10). The reason I say this is
that the clock networks on our Nios/Cyclone boards (one PLL for Nios,
fed back into a second to drive SDRAM) are slightly different than the
Stratix boards (only one PLL required for both an on-FPGA and external
SDRAM clock).

Also note: be sure to phase shift the external clock to SDRAM. If you
open up the example designs and take a look at the PLL you'll see what
I mean. This will compensate for board trace delay and should be
adjusted if you build your own board which, obviously, will have its
own delay.

Jesse Kempa
Altera Corp.
jkempa at altera dot com

Jesse/Ken,

Thanks for your responses. In fact I was debating whether or not
I needed one, but both your responses definitely eliminate my thought
of not having to implement one. I agree that this is required and
will definitely help me with any board skew as well. I haven't
implemented, but will look into the example and try to use some of the
results from that for the board. Do you know what the trace-lengths
(layout) is on the board to configure the proper phase delay
parameters for the PLL for the 1s10 NIOS eval.board? Is there a
recommended number I should use?

Regards,
Pino

 

[Jesse Kempa]

Jesse/Ken,

Thanks for your responses. In fact I was debating whether or not
I needed one, but both your responses definitely eliminate my thought
of not having to implement one. I agree that this is required and
will definitely help me with any board skew as well. I haven't
implemented, but will look into the example and try to use some of the
results from that for the board. Do you know what the trace-lengths
(layout) is on the board to configure the proper phase delay
parameters for the PLL for the 1s10 NIOS eval.board? Is there a
recommended number I should use?

Regards,
Pino

Look at the "standard" or "standard_32" design in Quartus and
double-click the PLL block to edit it. The wizard has several pages of
settings for the PLL. The one you are concerned with is the "Clock e0"
page, which lets you set a multiplier/divisor for the external clock
going to the PLL (the clock "c0" page lets you setup the clock that is
fed, in the example design, to SOPC Builder/Nios).

These settings let you set a phase shift in degrees or seconds; we
measured the delay between clock generation & signals arriving at
external SDRAM using an oscilloscope for our dev boards and that delay
is where the figure you see comes from. I'm looking at an example for
a 1s40 dev board now and its -3.5ns of shift. I recommend setting
shift in nanoseconds versus degrees of phase, because this way the
shift is constant even if you later tweak the clock speed of your
design.

Also, this PLL wizard is what you would use to change the clock speed
going to your SOPC Builder design (or other user logic).

- Jesse

 

[Pino]

kempaj@yahoo.com (Jesse Kempa) wrote in message news:<95776079.0407150807.5ca1b217@posting.google.com>...

Jesse/Ken,

Thanks for your responses. In fact I was debating whether or not
I needed one, but both your responses definitely eliminate my thought
of not having to implement one. I agree that this is required and
will definitely help me with any board skew as well. I haven't
implemented, but will look into the example and try to use some of the
results from that for the board. Do you know what the trace-lengths
(layout) is on the board to configure the proper phase delay
parameters for the PLL for the 1s10 NIOS eval.board? Is there a
recommended number I should use?

Regards,
Pino

Look at the "standard" or "standard_32" design in Quartus and
double-click the PLL block to edit it. The wizard has several pages of
settings for the PLL. The one you are concerned with is the "Clock e0"
page, which lets you set a multiplier/divisor for the external clock
going to the PLL (the clock "c0" page lets you setup the clock that is
fed, in the example design, to SOPC Builder/Nios).

These settings let you set a phase shift in degrees or seconds; we
measured the delay between clock generation & signals arriving at
external SDRAM using an oscilloscope for our dev boards and that delay
is where the figure you see comes from. I'm looking at an example for
a 1s40 dev board now and its -3.5ns of shift. I recommend setting
shift in nanoseconds versus degrees of phase, because this way the
shift is constant even if you later tweak the clock speed of your
design.

Also, this PLL wizard is what you would use to change the clock speed
going to your SOPC Builder design (or other user logic).

- Jesse

Setting the PLL to the correct phase delay helped. I now have a 100
MHz clock feeding my SDRAM module. I had started to implement the
PLL, but was not sure if this was exactly the right approach for
advancing the clock frequency. All your comments are very
appreciated!