Altera SOPC Master Peripheral Design?

[Pino]

I developed a custom state machine design as a Master Peripheral using
the Avalon Bus specifications. The purpose of this peripheral is to
read/write to external memory (i.e. SDRAM). I then include this in
SOPC Builder as a User-Defined Logic and define it as a Master
Peripheral and associate my top-level entity ports to the appropriate
names for the Avalon Bus. When I include the SDRAM controller as a
slave, the SOPC Builder indicates that the Master is not connected to
the slave, and the Slave is not connected to a Master. Since this is
an off-chip device, I include an Avalon Tri-state Bridge into SOPC
builder in order to allow SOPC Builder to automatically connect the
Master to the Slave. However, when I do so, the message window
indicates the contrary. The message I receive is as follows:

tri_state_bridge_0/avalon_slave is not connected to any Master.
Please connect it to a master of type avalon.

Note that the Master peripheral defined is of type avalon and so is
the SDRAM controller (as defined within the Memory devices in the
System Contents directory tree).

Can someone explain how I can properly connect a Master peripheral
(user-defined of course) to the SDRAM controller slave? Why does the
tristate bridge not allow this connection to occur?

P.S. If this same excercise is done using a NIOS processor master +
tristate bridge + SDRAM controller everything is connected with no
errors. The only difference that I see is that my Master is a
user-defined peripheral.


Regards,
Pino

 

[Jesse Kempa]

pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0406291101.30563548@posting.google.com>...
<snip>

tri_state_bridge_0/avalon_slave is not connected to any Master.
Please connect it to a master of type avalon.

Note that the Master peripheral defined is of type avalon and so is
the SDRAM controller (as defined within the Memory devices in the
System Contents directory tree).

Can someone explain how I can properly connect a Master peripheral
(user-defined of course) to the SDRAM controller slave? Why does the
tristate bridge not allow this connection to occur?

P.S. If this same excercise is done using a NIOS processor master +
tristate bridge + SDRAM controller everything is connected with no
errors. The only difference that I see is that my Master is a
user-defined peripheral.


Regards,
Pino

Hi Pino,

I believe the problem here is because of the various ways you can
construct a system with SDRAM. First, are you using Altera's SDRAM
controller that comes with Nios/SOPC Builder? Our controller has two
modes of operation with respect to its external pins:

1. No pin 'sharing'. This is the default behavior, and is what you'd
select if your board had I/O pins dedicated to SDRAM and SDRAM only.
In this mode, your master (or a CPU) connects directly to the SDRAM
controller. There should be no tri-state bridge in between (in fact,
SOPC Builder shouldn't let you make this connection legally, perhaps
this is where the issue is...)

2. SDRAM controller shares some of its pins with a tri-state bus. This
allows you to save FPGA I/O if your system also has some other
external memory (Flash, SRAM, etc.). Specifically the dq/dqm/address
pins are shared. This is activated with a checkbox in the SDRAM
controller GUI in SOPC Builder. In this mode, Avalon masters *must
also* directly connect to the controller (your logic, Nios, etc.), but
in addition, there will be a "More <sdram name> Settings" Page in SOPC
Builder that appears, and allows you to choose which (if more than
one) tri-state bridge you wish to route the shared I/O through. In
this case, the Avalon master/slave connections you make will be
similar to the first mode I described above: The master (your logic)
would connect directly to the SDRAM controller, in addition to the
tri-state bridge.

I just made a simple test-case to verify this using QII4.0/SOPCB4.0
and it generates fine/no warning messages. If you want, feel free to
email me and I will send you the system's files.

Jesse Kempa
Altera Corp.
jkempa at altera dot com

 

[Pino]

Jesse,

I sent you an e-mail directly but in case I would like to see
those system files if you have them. Although my suspicion is that
your file contains a NIOS master(cpu) which will function correctly
and allow SOPC builder to automatically connect the interfaces
seemlinglessly. However, I did not experience this with my designed
Master. All controllers (slave peripherals) used are directly from
Altera taken from within the SOPC builder system content menu. I am
aware of the two modes to configure the SDRAM, but neither functions
correctly with my master peripheral; however, only with the cpu (NIOS)
does it automatically connect with no errors. The question I still
ponder on is that whether you can indeed design a Master peripheral
using the Avalon Bus or does SOPC builder by default assume that the
only Master peripheral for the automatic connectivity is the "cpu" (ie
NIOS)? If you have a chance I sent you my Master.vhd file and you
can monitor the error I'm getting. Again, it's for this reason why I
have hypothesized my comment in the latter. Don't know if I have done
something erroneous.

Regards,
Pino

kempaj@yahoo.com (Jesse Kempa) wrote in message news:<95776079.0406300951.753e78cb@posting.google.com>...

pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0406291101.30563548@posting.google.com>...
snip

tri_state_bridge_0/avalon_slave is not connected to any Master.
Please connect it to a master of type avalon.

Note that the Master peripheral defined is of type avalon and so is
the SDRAM controller (as defined within the Memory devices in the
System Contents directory tree).

Can someone explain how I can properly connect a Master peripheral
(user-defined of course) to the SDRAM controller slave? Why does the
tristate bridge not allow this connection to occur?

P.S. If this same excercise is done using a NIOS processor master +
tristate bridge + SDRAM controller everything is connected with no
errors. The only difference that I see is that my Master is a
user-defined peripheral.


Regards,
Pino

Hi Pino,

I believe the problem here is because of the various ways you can
construct a system with SDRAM. First, are you using Altera's SDRAM
controller that comes with Nios/SOPC Builder? Our controller has two
modes of operation with respect to its external pins:

1. No pin 'sharing'. This is the default behavior, and is what you'd
select if your board had I/O pins dedicated to SDRAM and SDRAM only.
In this mode, your master (or a CPU) connects directly to the SDRAM
controller. There should be no tri-state bridge in between (in fact,
SOPC Builder shouldn't let you make this connection legally, perhaps
this is where the issue is...)

2. SDRAM controller shares some of its pins with a tri-state bus. This
allows you to save FPGA I/O if your system also has some other
external memory (Flash, SRAM, etc.). Specifically the dq/dqm/address
pins are shared. This is activated with a checkbox in the SDRAM
controller GUI in SOPC Builder. In this mode, Avalon masters *must
also* directly connect to the controller (your logic, Nios, etc.), but
in addition, there will be a "More <sdram name> Settings" Page in SOPC
Builder that appears, and allows you to choose which (if more than
one) tri-state bridge you wish to route the shared I/O through. In
this case, the Avalon master/slave connections you make will be
similar to the first mode I described above: The master (your logic)
would connect directly to the SDRAM controller, in addition to the
tri-state bridge.

I just made a simple test-case to verify this using QII4.0/SOPCB4.0
and it generates fine/no warning messages. If you want, feel free to
email me and I will send you the system's files.

Jesse Kempa
Altera Corp.
jkempa at altera dot com

 

[Pino]

kempaj@yahoo.com (Jesse Kempa) wrote in message news:<95776079.0406300951.753e78cb@posting.google.com>...

pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0406291101.30563548@posting.google.com>...
snip

tri_state_bridge_0/avalon_slave is not connected to any Master.
Please connect it to a master of type avalon.

Note that the Master peripheral defined is of type avalon and so is
the SDRAM controller (as defined within the Memory devices in the
System Contents directory tree).

Can someone explain how I can properly connect a Master peripheral
(user-defined of course) to the SDRAM controller slave? Why does the
tristate bridge not allow this connection to occur?

P.S. If this same excercise is done using a NIOS processor master +
tristate bridge + SDRAM controller everything is connected with no
errors. The only difference that I see is that my Master is a
user-defined peripheral.


Regards,
Pino

Hi Pino,

I believe the problem here is because of the various ways you can
construct a system with SDRAM. First, are you using Altera's SDRAM
controller that comes with Nios/SOPC Builder? Our controller has two
modes of operation with respect to its external pins:

1. No pin 'sharing'. This is the default behavior, and is what you'd
select if your board had I/O pins dedicated to SDRAM and SDRAM only.
In this mode, your master (or a CPU) connects directly to the SDRAM
controller. There should be no tri-state bridge in between (in fact,
SOPC Builder shouldn't let you make this connection legally, perhaps
this is where the issue is...)

2. SDRAM controller shares some of its pins with a tri-state bus. This
allows you to save FPGA I/O if your system also has some other
external memory (Flash, SRAM, etc.). Specifically the dq/dqm/address
pins are shared. This is activated with a checkbox in the SDRAM
controller GUI in SOPC Builder. In this mode, Avalon masters *must
also* directly connect to the controller (your logic, Nios, etc.), but
in addition, there will be a "More <sdram name> Settings" Page in SOPC
Builder that appears, and allows you to choose which (if more than
one) tri-state bridge you wish to route the shared I/O through. In
this case, the Avalon master/slave connections you make will be
similar to the first mode I described above: The master (your logic)
would connect directly to the SDRAM controller, in addition to the
tri-state bridge.

I just made a simple test-case to verify this using QII4.0/SOPCB4.0
and it generates fine/no warning messages. If you want, feel free to
email me and I will send you the system's files.

Jesse Kempa
Altera Corp.
jkempa at altera dot com

Jesse,

Thanks for the response. Just so you are aware I have only been
using the SDRAM controller from within the Altera library within the
system contents window. I have configured this slave peripheral as
per your option #2, and used the tristate bridge. In this particular
case, I do obtain something that SOPC can connect with no errors if
and only if I use a NIOS (cpu) master peripheral. If I use my
developed master peripheral, SOPC builder raises an error in that it
can not see the Master and highlights that it can not be connected to
it. This raises a question on whether or not I am able to use any
other master peripheral than the NIOS master peripheral? Does SOPC
builder recognize anything else? I have sent you my Master peripheral
"Master.VHD" file so that you can include this as "User defined Logic"
as a Avalon Master and monitor the type of error I have seen.

If anyone knows of any knows of anyway to connect a generic
Master peripheral using SOPC builder, this would be appreciated!


Regards,
Pino

 

[Pino]

pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0407011330.6a729843@posting.google.com>...

Jesse,

I sent you an e-mail directly but in case I would like to see
those system files if you have them. Although my suspicion is that
your file contains a NIOS master(cpu) which will function correctly
and allow SOPC builder to automatically connect the interfaces
seemlinglessly. However, I did not experience this with my designed
Master. All controllers (slave peripherals) used are directly from
Altera taken from within the SOPC builder system content menu. I am
aware of the two modes to configure the SDRAM, but neither functions
correctly with my master peripheral; however, only with the cpu (NIOS)
does it automatically connect with no errors. The question I still
ponder on is that whether you can indeed design a Master peripheral
using the Avalon Bus or does SOPC builder by default assume that the
only Master peripheral for the automatic connectivity is the "cpu" (ie
NIOS)? If you have a chance I sent you my Master.vhd file and you
can monitor the error I'm getting. Again, it's for this reason why I
have hypothesized my comment in the latter. Don't know if I have done
something erroneous.

Regards,
Pino

kempaj@yahoo.com (Jesse Kempa) wrote in message news:<95776079.0406300951.753e78cb@posting.google.com>...
pinod01@sympatico.ca (Pino) wrote in message news:<b7ed9648.0406291101.30563548@posting.google.com>...
snip

tri_state_bridge_0/avalon_slave is not connected to any Master.
Please connect it to a master of type avalon.

Note that the Master peripheral defined is of type avalon and so is
the SDRAM controller (as defined within the Memory devices in the
System Contents directory tree).

Can someone explain how I can properly connect a Master peripheral
(user-defined of course) to the SDRAM controller slave? Why does the
tristate bridge not allow this connection to occur?

P.S. If this same excercise is done using a NIOS processor master +
tristate bridge + SDRAM controller everything is connected with no
errors. The only difference that I see is that my Master is a
user-defined peripheral.


Regards,
Pino

Hi Pino,

I believe the problem here is because of the various ways you can
construct a system with SDRAM. First, are you using Altera's SDRAM
controller that comes with Nios/SOPC Builder? Our controller has two
modes of operation with respect to its external pins:

1. No pin 'sharing'. This is the default behavior, and is what you'd
select if your board had I/O pins dedicated to SDRAM and SDRAM only.
In this mode, your master (or a CPU) connects directly to the SDRAM
controller. There should be no tri-state bridge in between (in fact,
SOPC Builder shouldn't let you make this connection legally, perhaps
this is where the issue is...)

2. SDRAM controller shares some of its pins with a tri-state bus. This
allows you to save FPGA I/O if your system also has some other
external memory (Flash, SRAM, etc.). Specifically the dq/dqm/address
pins are shared. This is activated with a checkbox in the SDRAM
controller GUI in SOPC Builder. In this mode, Avalon masters *must
also* directly connect to the controller (your logic, Nios, etc.), but
in addition, there will be a "More <sdram name> Settings" Page in SOPC
Builder that appears, and allows you to choose which (if more than
one) tri-state bridge you wish to route the shared I/O through. In
this case, the Avalon master/slave connections you make will be
similar to the first mode I described above: The master (your logic)
would connect directly to the SDRAM controller, in addition to the
tri-state bridge.

I just made a simple test-case to verify this using QII4.0/SOPCB4.0
and it generates fine/no warning messages. If you want, feel free to
email me and I will send you the system's files.

Jesse Kempa
Altera Corp.
jkempa at altera dot com

Just thought I'd provide a quick follow-up and a thanks to Jesse for
the help. Others may be reading this and would be of interest. It
seems there are several things to do when creating a Master peripheral

1 - I was assigning a bidirectional pin for reading & writing to
memory. This is incorrect and as per the Avalon specifications, there
must be a unidirection pin for both a read and a write.

2 - apparently you do not need the tristate bridge to be included in
teh SOPC builder design. This is used only for external off-chip
buses. In my case, I only wanted to have a connection to the SDRAM.
Therefore, you must select the option within the SDRAM controller in
the System Wizard to "NO shared pins".

These two steps make the difference and allows you to compile the
generated code.