[Altera/Quartus] Tools to regenerate block schematics from .

[Pszemol]

I am kind of new to FPGA design and I have to understand a circuit given
as a set of hierarchical .vhd files (top level and two-three lower levels),
but it would be kind of nice to see it layed out on a piece of paper...
Is there a tool to generate schematics from vhd files to visualize vhd?

 

[Rene Tschaggelar]

Pszemol wrote:

I am kind of new to FPGA design and I have to understand a circuit given
as a set of hierarchical .vhd files (top level and two-three lower levels),
but it would be kind of nice to see it layed out on a piece of paper...
Is there a tool to generate schematics from vhd files to visualize vhd?

As I understood it, the schematic approach and the VHDL approach
are not necessarily equivalent. Meaning not every line of code
can be shown as schematic.
Eg statemachines are supposed not to be displayable in schematics.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[Fredrik]

Hi Pszemol,
You have the RTL view in Quartus that will short of do this for you.
RTL means that you will see it at a very basic level, flip-flops,
Luts,muxs and soforth. Alltough the RTL viewer build up a hirachy from
your VHDL files so you are going to see the top enties in the first
view anyhow. I think also some 3arty tools have this
features.(simplify?) This is a new feature as of Quartus2_ver4 so it
might not be avalible in the free version of the tool.
Cheers
Fredrik
Rene Tschaggelar <none@none.net> wrote in message news:<4028b69a$0$708$5402220f@news.sunrise.ch>...

Pszemol wrote:

I am kind of new to FPGA design and I have to understand a circuit given
as a set of hierarchical .vhd files (top level and two-three lower levels),
but it would be kind of nice to see it layed out on a piece of paper...
Is there a tool to generate schematics from vhd files to visualize vhd?

As I understood it, the schematic approach and the VHDL approach
are not necessarily equivalent. Meaning not every line of code
can be shown as schematic.
Eg statemachines are supposed not to be displayable in schematics.

Rene

 

[Pszemol]

"Fredrik" <fredrik_he_lang@hotmail.com> wrote in message news:77a94d51.0402100656.26670ade@posting.google.com...

You have the RTL view in Quartus that will short of do this for you.
RTL means that you will see it at a very basic level, flip-flops,
Luts,muxs and soforth. Alltough the RTL viewer build up a hirachy from
your VHDL files so you are going to see the top enties in the first
view anyhow.

This is the only thing I want right now.

I think also some 3arty tools have this features.(simplify?)
This is a new feature as of Quartus2_ver4 so it
might not be avalible in the free version of the tool.

I have version 3, so I guess I need to request an upgrade.
Thanks.

 

[sesh67]

"Pszemol" <Pszemol@PolBox.com> wrote in message news:<c0acsk.3oc.0@poczta.onet.pl>...

"Fredrik" <fredrik_he_lang@hotmail.com> wrote in message news:77a94d51.0402100656.26670ade@posting.google.com...
You have the RTL view in Quartus that will short of do this for you.
RTL means that you will see it at a very basic level, flip-flops,
Luts,muxs and soforth. Alltough the RTL viewer build up a hirachy from
your VHDL files so you are going to see the top enties in the first
view anyhow.

This is the only thing I want right now.

I think also some 3arty tools have this features.(simplify?)
This is a new feature as of Quartus2_ver4 so it
might not be avalible in the free version of the tool.

I have version 3, so I guess I need to request an upgrade.
Thanks.

RTL viewer is available with the full version of the Quartus II
version 4.0 software. For details on RTL viewer, check the Quartus II
Handbook chapter
http://www.altera.com/literature/hb/qts/qts_qii51013.pdf

Regards,
Seshan
Altera Corp.