P
peter dudley
Guest
Hello,
I like to be able to instantiate FPGA primitives directly in my VHDL in order to get fine control of a design and to get full access to the hardware features of the chip.
Xilinx publishes libraries for each family of parts, for example "7 Series Libraries Guide for HDL Designs". These guides describe how to instantiate and parameterize every component available in the part. This is good for block RAMs, PLLs, I/O SerDes, etc.
Does something like this exist for Altera devices?
Sometimes I use Xilinx Logicore or Altera Megafunction generators but often I need to get right to the elements of the chip.
Thanks for any advice.
Pete
I like to be able to instantiate FPGA primitives directly in my VHDL in order to get fine control of a design and to get full access to the hardware features of the chip.
Xilinx publishes libraries for each family of parts, for example "7 Series Libraries Guide for HDL Designs". These guides describe how to instantiate and parameterize every component available in the part. This is good for block RAMs, PLLs, I/O SerDes, etc.
Does something like this exist for Altera devices?
Sometimes I use Xilinx Logicore or Altera Megafunction generators but often I need to get right to the elements of the chip.
Thanks for any advice.
Pete