Altera EP2C8A -- dead PLL

[Philip Pemberton]

Here's a head-scratcher.

I have five boards with an Altera EP2C8AT144 FPGA and a Microchip
PIC18F85J50 installed. Specifically, these are DiscFerrets: <http://
www.discferret.com>.

Two of these boards have an "issue". The PLL won't work. At all. The
LOCKED output stays low, and there's absolutely nothing on the clock
output.

Does anyone have any ideas why the PLLs might behave like this?
As near as I can tell (based on a continuity and voltage check with a
DMM), the PLL VCCs and grounds are all OK.

Bypassing consists of a 10nf X7R on every Vcc or Vcore pin (yes, every
single one!) plus a 100uF on the output of the SMPSU. There are also
several 100nF capacitors on the same rail a few inches away, decoupling
the power for the PIC.


Thanks,
--
Phil.
usenet10@philpem.me.uk
http://www.philpem.me.uk/
If mail bounces, replace "10" with the last two digits of the current year

 

[Nial Stewart]

Two of these boards have an "issue". The PLL won't work. At all. The
LOCKED output stays low, and there's absolutely nothing on the clock
output.

How are you implementing the PLLs?

ISTR that you can have a reset input (that I don't usually use). You
haven't left this in have you?

Does anyone have any ideas why the PLLs might behave like this?
As near as I can tell (based on a continuity and voltage check with a
DMM), the PLL VCCs and grounds are all OK.

On the web site you say...

"This power supply is designed to bring up the 1.2V supply first: this
is the core voltage for the FPGA, and it is essential that this be stable
before the 3.3V I/O power supply is started."

Are you sure about this, Altera devices aren't usually fussy about power
sequencing but there _are_ some requirements about total power on delay (if
I remember correctly).

Can you remove the power on delays and just let everything come up as
quickly as possible on one of these boards to see if that makes
any difference?

Are the devices getting at all hot?


Nial.

 

[Philip Pemberton]

On Wed, 24 Nov 2010 15:31:01 +0000, Nial Stewart wrote:

Two of these boards have an "issue". The PLL won't work. At all. The
LOCKED output stays low, and there's absolutely nothing on the clock
output.

How are you implementing the PLLs?

Input, two clock outputs, and a LOCKED output. No reset input, all built
with the MegaFunction Builder.

Input is 20MHz, outputs are 32MHz on OUT0 and 80MHz on OUT1.

"This power supply is designed to bring up the 1.2V supply first: this
is the core voltage for the FPGA, and it is essential that this be
stable before the 3.3V I/O power supply is started."

Are you sure about this, Altera devices aren't usually fussy about power
sequencing but there _are_ some requirements about total power on delay
(if I remember correctly).

This is a relic from when I was designing around another part which did
require that 1V2 come up before VIO. If VIO came up before 1V2, the part
let out the magic smoke.

Shoddy development tools and poor availability ended my love affair with
that part (though it was marginally little cheaper than the Cyclone2)...

Can you remove the power on delays and just let everything come up as
quickly as possible on one of these boards to see if that makes any
difference?

Not easily. I'd have to perform microsurgery on a few 7mil pitch tracks
around the power controller chip. There's only a few mm of clearance
around that thing -- it's just about possible to replace with hot air, or
get a piece of solder wick in to clear a bridged pad...

Are the devices getting at all hot?

No. Nothing on the board is running at above ambient (they're cold to the
touch). Utilisation on the FPGA is in the high single-digit percentage
points, though -- only 8% of the LEs (654 of 8256) are in use.

Thanks,
--
Phil.
usenet10@philpem.me.uk
http://www.philpem.me.uk/
If mail bounces, replace "10" with the last two digits of the current year

 

[KJ]

On Nov 24, 12:28 pm, Philip Pemberton <usene...@philpem.me.uk> wrote:

No. Nothing on the board is running at above ambient (they're cold to the
touch). Utilisation on the FPGA is in the high single-digit percentage
points, though -- only 8% of the LEs (654 of 8256) are in use.

The only thing that should stop the PLLs are:
- Power (check with a scope too at the pin of the part, not just with
a DMM just in case)
- Clock (again, check at the pin)
- Bitstream not getting loaded correctly (Do the configuration control
and status signals all look proper?)
- Held in reset
- Bum parts

KJ

 

[Philip Pemberton]

On Wed, 24 Nov 2010 09:40:29 -0800, KJ wrote:

The only thing that should stop the PLLs are: - Power (check with a
scope too at the pin of the part, not just with a DMM just in case)

Ah HA!

I just found high-resistance (i.e. "dry") solder joints on the PLL VCC
lines. Resoldered, and the PLLs are running. Now I just have a dozen or
so RAM Address Line Fault errors to resolve (i.e. flux the pins up good
'n' proper, and hit the little SOBs with a soldering iron).

Well, it's one for the "possible faults" list at least.

--
Phil.
usenet10@philpem.me.uk
http://www.philpem.me.uk/
If mail bounces, replace "10" with the last two digits of the current year