Altera DSP builder problem with delay and Integrator

[Jacob Sřrensen]

Hi

Just wanted to here if anyone has an idea to what I am doing wrong.

I can not get the integrator and delay components to work in the DSP
builder.

All the Arithmetic and gates blocks I use, works well, and the FIFO
storage element workd well too.

Any suggestions are most welcome.

/Jacob
--

Msg. From Jacob Soerensen
jacob@jacob-s.net
http://jacob-s.net

Nothing in nature is random ...
A thing appears random only through the incompleteness of our
knowledge. Spinoza, Ethics I

 

[Hong Shan Neoh]

The integrator is based on the equation q=q+d. If it is a simulation
problem in Simulink, make sure your simulation parameters (i.e. Solver
Options, Single tasking mode etc.) and sampling rate for your source
block are set correctly.

There is an design example of a CIC filter which shows you how the
integrator block can be incorporated into your design. The design is
located in the
following directory: <installation_path>\DSPBuilder\designexamples


-HS
hneoh@altera.com

Jacob@jacob-s.net (Jacob Sřrensen) wrote in message news:<2n4fzdvoi36.fsf@jacob-s.net>...

Hi

Just wanted to here if anyone has an idea to what I am doing wrong.

I can not get the integrator and delay components to work in the DSP
builder.

All the Arithmetic and gates blocks I use, works well, and the FIFO
storage element workd well too.

Any suggestions are most welcome.

/Jacob
--

Msg. From Jacob Soerensen
jacob@jacob-s.net
http://jacob-s.net

Nothing in nature is random ...
A thing appears random only through the incompleteness of our
knowledge. Spinoza, Ethics I

 

[Jacob Sřrensen]

I have no problem in the simulation, her it works as I expected.

I have also checked that all source blocks are set to the actual
samplings frequency.

I seem to be a problem with clocking data in and/or out of the
integrator. All other blocks in the model works fine. When I implement
the model as symbol file and include it in my quartuss project.

/Jacob

"Hong" == Hong Shan Neoh <hsneoh@netscape.net> writes:

Hong> The integrator is based on the equation q=q+d. If it is a
Hong> simulation problem in Simulink, make sure your simulation
Hong> parameters (i.e. Solver Options, Single tasking mode etc.) and
Hong> sampling rate for your source block are set correctly.

Hong> There is an design example of a CIC filter which shows you how
Hong> the integrator block can be incorporated into your design. The
Hong> design is located in the following directory:
Hong> <installation_path>\DSPBuilder\designexamples


Hong> -HS hneoh@altera.com

Hong> Jacob@jacob-s.net (Jacob Sřrensen) wrote in message
Hong> news:<2n4fzdvoi36.fsf@jacob-s.net>...

Hi

Just wanted to here if anyone has an idea to what I am doing wrong.

I can not get the integrator and delay components to work in the
DSP builder.

All the Arithmetic and gates blocks I use, works well, and the FIFO
storage element workd well too.

Any suggestions are most welcome.

/Jacob --

Msg. From Jacob Soerensen jacob@jacob-s.net http://jacob-s.net

Nothing in nature is random ... A thing appears random only
through the incompleteness of our knowledge. Spinoza, Ethics I

--

Msg. From Jacob Soerensen
jacob@jacob-s.net
http://jacob-s.net

Nothing in nature is random ...
A thing appears random only through the incompleteness of our
knowledge. Spinoza, Ethics I

 

[Hong Shan Neoh]

I would suggest isolating the block and making sure you are able
to simulate the VHDL netlist in ModelSim using the automated
testbench and script generated by Signal Compiler.

You should also submit your design to the technical support group
(mysupport.altera.com) in order for us to debug this problem further.


-HS
hneoh@altera.com

 

[Jacob Sřrensen]

Yes I allready send a request to the mySupport system at Altera, but
now it seems I will have to cancel it, because I had connected the
sclrp connection to the block wrong in the Quartus design, just found
out last night. I am new to this, so there is many more mistakes to be
made yet.

Thanks for the advice.

/Jacob

"Hong" == Hong Shan Neoh <hsneoh@netscape.net> writes:

Hong> I would suggest isolating the block and making sure you are able
Hong> to simulate the VHDL netlist in ModelSim using the automated
Hong> testbench and script generated by Signal Compiler.

Hong> You should also submit your design to the technical support
Hong> group (mysupport.altera.com) in order for us to debug this
Hong> problem further.


Hong> -HS hneoh@altera.com

--

Msg. From Jacob Soerensen
jacob@jacob-s.net
http://jacob-s.net

Nothing in nature is random ...
A thing appears random only through the incompleteness of our
knowledge. Spinoza, Ethics I