Altera Cyclone II

[Michael]

Hi,

I have a Altera Cyclone II design where I am looking for a good way to
make a complete reset via HDL.

In Xilinx there is a STARTUP macro that can be used for reset, does the
Altera also have a similar macro or other way to via HDL make a complete
reset?

cheers

Michael

 

[kaz]

Hi,

I have a Altera Cyclone II design where I am looking for a good way to
make a complete reset via HDL.

In Xilinx there is a STARTUP macro that can be used for reset, does the
Altera also have a similar macro or other way to via HDL make a complete
reset?

cheers

Michael

Altera does not recommend internal reset if that is what you mean. Thoug
you can
design one simply by running a counter from zero to some value and sto
then
apply/release reset according to counter value. This requires zero startu
which is can
be guaranteed after fpga chipwide reset release but may fail due t
possibility of timing
violation as external clock could arrive any time.

Kaz

---------------------------------------
Posted through http://www.FPGARelated.com

 

[Michael]

Hi,
On 01/15/15 07:26 PM, kaz wrote:

Hi,

I have a Altera Cyclone II design where I am looking for a good way to
make a complete reset via HDL.

In Xilinx there is a STARTUP macro that can be used for reset, does the
Altera also have a similar macro or other way to via HDL make a complete
reset?

cheers

Michael


Altera does not recommend internal reset if that is what you mean. Though
you can
design one simply by running a counter from zero to some value and stop
then
apply/release reset according to counter value. This requires zero startup
which is can
be guaranteed after fpga chipwide reset release but may fail due to
possibility of timing
violation as external clock could arrive any time.

Kaz

---------------------------------------
Posted through http://www.FPGARelated.com

The Xilinx startup macro connects to the FPGAs internal reset net which
means triggering the reset via the macro generates a powerup reset just
like after configuration. This means that even FF that do not have a HDL
reset net will get back to its initial state.

This is very handy. I was hoping that I could generate a reset in the
Cyclone II in the same way without adding alot of code to all process.

anyhow, thanks for the reply

Michael

 

[Adam GĂłrski]

On 2015-01-15 08:19, Michael wrote:

Hi,

I have a Altera Cyclone II design where I am looking for a good way to
make a complete reset via HDL.

In Xilinx there is a STARTUP macro that can be used for reset, does the
Altera also have a similar macro or other way to via HDL make a complete
reset?

cheers

Michael

http://www.alteraforum.com/forum/showthread.php?t=24658

Adam GĂłrski

 

[Tomas D.]

"Michael" <michael_laajanen@yahoo.com> wrote in message
news:chp7vjFof2bU1@mid.individual.net...

Hi,

I have a Altera Cyclone II design where I am looking for a good way to
make a complete reset via HDL.

In Xilinx there is a STARTUP macro that can be used for reset, does the
Altera also have a similar macro or other way to via HDL make a complete
reset?

cheers

Michael

Hello Michael,
you have two options:
1) If you use PLL, then use LOCKED output as a reset to your logic. Create a
counter, that will set PLL areset input to high when you need a reset.
2) A hardware reset by routing IO pin to nCONFIG input, which would have a
pull-up resistor. When the FPGA is reseted, the pull-up would ensure the
nCONFIG is high and the FPGA can enter user mode. When user-mode is reached,
the output is kept high until the reset is needed. This will reset the FPGA
completely.

Regards
Tomas D.

 

[KJ]

On Monday, January 19, 2015 at 3:54:33 PM UTC-5, Tomas D. wrote:

"Michael" <michael_...@yahoo.com> wrote in message

you have two options:
1) If you use PLL, then use LOCKED output as a reset to your logic. Create a
counter, that will set PLL areset input to high when you need a reset.

This won't do what the OP asked. What was asked was a way to reset all of the flip flops. Reseting the PLL in order to cause it to unlock won't do that. All it will do is shut off the clocks for a period of time until the PLLs come back online. That by itself does absolutely nothing to any of the flip flops. You're presuming that the 'locked' PLL output is already being explicitly used to reset every flip flop in the design either directly or through some reset code in the FPGA design, but a simple 'D' flip flop will not react at all.

Q <= D when rising_edge(Clock);

2) A hardware reset by routing IO pin to nCONFIG input, which would have a
pull-up resistor. When the FPGA is reseted, the pull-up would ensure the
nCONFIG is high and the FPGA can enter user mode. When user-mode is reached,
the output is kept high until the reset is needed. This will reset the FPGA
completely.

Perusal of the datasheet shows that this approach is not guaranteed to work.. The datasheet specifies a maximum of 800 ns from nConfig low to Conf_Done low as well as a minimum of 2 us for nConfig to stay low. So you can only count on the FPGA to produce a maximum low time on nConfig of less than half the required minimum.

Also, this approach goes too far in that not only are the flip flops reset (as was requested), but the entire FPGA has now lost it's configuration and is brain dead. To recover, the FPGA will need to be reconfigured which means that whatever circuit that responds to some external event that causes FPGA configuration to occur in the first place (like powerup in many designs) needs to be restarted. The configuration circuit would have to monitor Conf_Done and look for a high to low transition to cause it to once again configure the FPGA.

Kevin Jennings

 

[Michael]

Hi,
On 01/19/15 09:54 PM, Tomas D. wrote:

"Michael" <michael_laajanen@yahoo.com> wrote in message
news:chp7vjFof2bU1@mid.individual.net...
Hi,

snip

Hello Michael,
you have two options:
1) If you use PLL, then use LOCKED output as a reset to your logic. Create a
counter, that will set PLL areset input to high when you need a reset.
2) A hardware reset by routing IO pin to nCONFIG input, which would have a
pull-up resistor. When the FPGA is reseted, the pull-up would ensure the
nCONFIG is high and the FPGA can enter user mode. When user-mode is reached,
the output is kept high until the reset is needed. This will reset the FPGA
completely.

Regards
Tomas D.


Thanks Tomas, I will start with the first suggestion.

cheers

Michael

 

[Adam Górski]

Hello Michael,
you have two options:
1) If you use PLL, then use LOCKED output as a reset to your logic.
Create a
counter, that will set PLL areset input to high when you need a reset.


Regards
Tomas D.


Thanks Tomas, I will start with the first suggestion.

Hello,

Be careful using PLL lock signal. PLL once locked is NOT locked forever
and re-lock may occurs. See documentation.

BR

Adam

 

Initialize up-counters to even values, and the maximum synchronization error is 1 for an asynchronously released reset.

Andy