Altera Cyclone data is incomplete or messy

[Rene Tschaggelar]

Browsing the 'cyclone device handbook' I spent a great
length to find :
-the max current for each supply ( VCCIO & VCCINT )
-the expected clocking frequency at the input. I'm aware
that 1MHz may not be sufficient to PLL it up to 400MHz
or such.

to little avail. While I can live with 2 switchmode supplies
generating 1.5V and 3.3V at 2A each, and a generic 8pin
socket to swap oscillators for a prototype, the documentation
is somehow inclomplete.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[Ralph Malph]

Rene Tschaggelar wrote:

Browsing the 'cyclone device handbook' I spent a great
length to find :
-the max current for each supply ( VCCIO & VCCINT )
-the expected clocking frequency at the input. I'm aware
that 1MHz may not be sufficient to PLL it up to 400MHz
or such.

to little avail. While I can live with 2 switchmode supplies
generating 1.5V and 3.3V at 2A each, and a generic 8pin
socket to swap oscillators for a prototype, the documentation
is somehow inclomplete.

I don't think anyone publishes a *max* current for FPGAs. This depends
greatly on the design and the clock speed. It even depends on the
loading on the IO lines. But one way you can set a ceiling is to figure
out the maximum dissipation the package can provide and assume that can
come from either of the two supplies. The may be very conservative, but
it will give you a *maximum*.

 

[Nial Stewart]

Rene Tschaggelar <none@none.none> wrote in message
news:41c489438e778508c6ca433ed9cabaf5@news.teranews.com...

Browsing the 'cyclone device handbook' I spent a great
length to find :
-the max current for each supply ( VCCIO & VCCINT )

Rene, there's a power consumption spreadsheet
downloadable for the Cyclone which will give you
figures for your application.

-the expected clocking frequency at the input. I'm aware
that 1MHz may not be sufficient to PLL it up to 400MHz
or such.

The PLL output is
Input MHz * M/(N * post_scale_counter)
where M = 2 to 32, N and post_scale_counter = 1 to 32

I'm pretty sure I got this from the data sheets.

Have you checked you've got the latest version, they seem
to update them fairly regularly.


Nial Stewart
------------------------------------------------
Nial Stewart Developments Ltd
FPGA and High Speed Digital Design
Cyclone based 'Easy PCI' dev board
www.nialstewartdevelopments.co.uk

 

[Rene Tschaggelar]

Ralph Malph wrote:

Rene Tschaggelar wrote:

Browsing the 'cyclone device handbook' I spent a great
length to find :
-the max current for each supply ( VCCIO & VCCINT )
-the expected clocking frequency at the input. I'm aware
that 1MHz may not be sufficient to PLL it up to 400MHz
or such.

to little avail. While I can live with 2 switchmode supplies
generating 1.5V and 3.3V at 2A each, and a generic 8pin
socket to swap oscillators for a prototype, the documentation
is somehow inclomplete.


I don't think anyone publishes a *max* current for FPGAs. This depends
greatly on the design and the clock speed. It even depends on the
loading on the IO lines. But one way you can set a ceiling is to figure
out the maximum dissipation the package can provide and assume that can
come from either of the two supplies. The may be very conservative, but
it will give you a *maximum*.

At least the earlier Altera FPGAs had graphs. Usually 1/8 th of the
cells used, current vs clock. Just multiply by 8 and you're about
there.

I somewhat doubt everyone makes the prototypes with leads to be
connected to a laboratory power supply.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[Hal Murray]

I don't think anyone publishes a *max* current for FPGAs. This depends
greatly on the design and the clock speed. It even depends on the
loading on the IO lines. But one way you can set a ceiling is to figure
out the maximum dissipation the package can provide and assume that can
come from either of the two supplies. The may be very conservative, but
it will give you a *maximum*.

Does that really get you a max?

Suppose heat is the limiting factor on the FPGA, but I run it in
a pulse mode. It's active 10% of the time, but working real hard
when it's active. The length of the active burst can be long
enough to cause trouble for the power supply if it's only beefy
enough for the average.

--
The suespammers.org mail server is located in California. So are all my
other mailboxes. Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's. I hate spam.

 

[Vaughn Betz]

Rene Tschaggelar <none@none.none> wrote in message news:<41c489438e778508c6ca433ed9cabaf5@news.teranews.com>...

Browsing the 'cyclone device handbook' I spent a great
length to find :
-the max current for each supply ( VCCIO & VCCINT )
-the expected clocking frequency at the input. I'm aware
that 1MHz may not be sufficient to PLL it up to 400MHz
or such.

to little avail. While I can live with 2 switchmode supplies
generating 1.5V and 3.3V at 2A each, and a generic 8pin
socket to swap oscillators for a prototype, the documentation
is somehow inclomplete.

Rene

Hi Rene,

See section 4 of the Cyclone device handbook. (Available at
http://www.altera.com/literature/hb/cyc/cyc_c51004.pdf). Page 4-8
gives the current & power during configuration, and refers you to the
Cyclone power calculator spreadsheet for doing what-if analysis on
application circuits power and current needs while they're running.

That spreadsheet is at:
http://www.altera.com/products/devices/cyclone/utilities/power_calculator/cyc-power_calculator.html

You'll have to enter what you think are reasonable worst-case numbers
in terms of operating frequency, toggle rate, IO standards used etc.
to get the current supply info you need.

Page 4-31 of the device handbook gives the PLL frequency specs. The
input frequency has to be between 15.625 MHz and 464 MHz for the
fastest (-6) speed grade, and between 15.625 MHz and 387 MHz for the
slowest (-8) speed grade. See
http://www.altera.com/literature/hb/cyc/cyc_c51004.pdf for details.

Regards,

Vaughn
Altera

 

[Rene Tschaggelar]

Vaughn Betz wrote:

Rene Tschaggelar <none@none.none> wrote in message news:<41c489438e778508c6ca433ed9cabaf5@news.teranews.com>...

Browsing the 'cyclone device handbook' I spent a great
length to find :
-the max current for each supply ( VCCIO & VCCINT )
-the expected clocking frequency at the input. I'm aware
that 1MHz may not be sufficient to PLL it up to 400MHz
or such.

to little avail. While I can live with 2 switchmode supplies
generating 1.5V and 3.3V at 2A each, and a generic 8pin
socket to swap oscillators for a prototype, the documentation
is somehow inclomplete.

Hi Rene,

See section 4 of the Cyclone device handbook. (Available at
http://www.altera.com/literature/hb/cyc/cyc_c51004.pdf). Page 4-8
gives the current & power during configuration, and refers you to the
Cyclone power calculator spreadsheet for doing what-if analysis on
application circuits power and current needs while they're running.

Thanks. I saw the maximum configuration currents but found them
not really usefull for a non-powersaving application.
I admittedly only scanned the document for 'mA'.

That spreadsheet is at:
http://www.altera.com/products/devices/cyclone/utilities/power_calculator/cyc-power_calculator.html

You'll have to enter what you think are reasonable worst-case numbers
in terms of operating frequency, toggle rate, IO standards used etc.
to get the current supply info you need.

Thanks. Neither really binding numbers as liability is denied, nor useable
without Excel. I'll be warned. I'll start with a pcb prototype where some
space is reserved for heatsink mounting holes plus some screw power terminals
in case the 2A switcher comes to its limit.

Page 4-31 of the device handbook gives the PLL frequency specs. The
input frequency has to be between 15.625 MHz and 464 MHz for the
fastest (-6) speed grade, and between 15.625 MHz and 387 MHz for the
slowest (-8) speed grade. See
http://www.altera.com/literature/hb/cyc/cyc_c51004.pdf for details.

Thanks. These numbers somehow slipped me, even though I scanned the document
for 'PLL'. Too many occurences of it, I guess.

Rene

 

[Ralph Malph]

Hal Murray wrote:

I don't think anyone publishes a *max* current for FPGAs. This depends
greatly on the design and the clock speed. It even depends on the
loading on the IO lines. But one way you can set a ceiling is to figure
out the maximum dissipation the package can provide and assume that can
come from either of the two supplies. The may be very conservative, but
it will give you a *maximum*.

Does that really get you a max?

Suppose heat is the limiting factor on the FPGA, but I run it in
a pulse mode. It's active 10% of the time, but working real hard
when it's active. The length of the active burst can be long
enough to cause trouble for the power supply if it's only beefy
enough for the average.

So then you know that this is the case and you will adjust the
calculations accordingly, right?

 

[Peter Alfke]

That posting suggested to deduce the max operating power backwards from
the package thermal resistance.
Do NOT do that !
Package choice is dominated by cost and price consideration, both on the
part of the chip manufacturer and on the part of the user.
To make the assumption "because it comes in this high thermal resistance
package, it will never dissipate more than x Watts" is, excuse the
word, silly.
Most FPGAs these days can be melted down by a crazy (but legitimate)
design running at an outrageous ( but legitimate) clock frequency.
It's up to the user to keep the junction temperature within spec. All we
manufacturers can do is give you the best analysis tools we can come up with...
Peter Alfke, Xilinx
=============================
Ralph Malph wrote:

But one way you can set a ceiling is to figure
out the maximum dissipation the package can provide and assume that can come from either of the two supplies. The may be very conservative, but
it will give you a *maximum*.

 

[Rene Tschaggelar]

Peter Alfke wrote:

That posting suggested to deduce the max operating power backwards from
the package thermal resistance.
Do NOT do that !
Package choice is dominated by cost and price consideration, both on the
part of the chip manufacturer and on the part of the user.
To make the assumption "because it comes in this high thermal resistance
package, it will never dissipate more than x Watts" is, excuse the
word, silly.
Most FPGAs these days can be melted down by a crazy (but legitimate)
design running at an outrageous ( but legitimate) clock frequency.
It's up to the user to keep the junction temperature within spec. All we
manufacturers can do is give you the best analysis tools we can come up with...

Thanks Peter,
the first sensible answer. What is wrong with a simple formula ?
Eg Imax = Io + 4mA/Mhz + I/O_load.

It'd help specifying the power supply as well as the heatsink.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[Ralph Malph]

Peter Alfke wrote:

That posting suggested to deduce the max operating power backwards from
the package thermal resistance.
Do NOT do that !
Package choice is dominated by cost and price consideration, both on the
part of the chip manufacturer and on the part of the user.
To make the assumption "because it comes in this high thermal resistance
package, it will never dissipate more than x Watts" is, excuse the
word, silly.
Most FPGAs these days can be melted down by a crazy (but legitimate)
design running at an outrageous ( but legitimate) clock frequency.
It's up to the user to keep the junction temperature within spec. All we
manufacturers can do is give you the best analysis tools we can come up with...
Peter Alfke, Xilinx
=============================
Ralph Malph wrote:
But one way you can set a ceiling is to figure
out the maximum dissipation the package can provide and assume that can come from either of the two supplies. The may be very conservative, but
it will give you a *maximum*.

No one said that Peter. The termal characteristics limit the power that
can be used in a given chip. So if you are sizing the power supply,
then this is a realistic number to go by. If a user wants to put a
higher power design in the FPGA, then it might even be a good idea for
the power supply to limit the power at the package level.

Keep in mind the purpose of the discussion, to size the power supply.

 

[Peter Alfke]

Rene Tschaggelar wrote:

Thanks Peter,
the first sensible answer. What is wrong with a simple formula ?
Eg Imax = Io + 4mA/Mhz + I/O_load.

It'd help specifying the power supply as well as the heatsink.

Rene, unfortunately it is not that simple.
• Io is just the static leakage current, which tends to be
junction-temperature dependent, and unfortunately has increased
dramatically with 130 and 90 nm technology. Like a hundred times :-(
• mA per MHz depends on the frequency of each node, times the
capacitance of that node, and all this accumulated over the whole chip.
Some people (notably our friendly A competitor) make the tacit
assumption that everything behaves like a 16-bit counter, But that can
lead to very optimistic results, compared to a real DSP-like circuit
where everything is clocked at 300 MHz, and half the flip-flops and
interconnects change each clock period.
• I/O load is usually not static, but rather a load driving board- and
input capacitances. So you again need the capacitance and average
frequency of each pin.

This is why power calculation is such a chore.
On top of this, a 50% tolerance guess is no good. You don't want to
guardband your supply by a factor 2, and you definitely cannot be wrong
by a factor 2 when you calculate the junction over-temperature.
Theoretically, you have only between 50 (?) degrees max inside the box,
and 85 degrees at the junction. There is not much room to make a
mistake and accept an error or even a widetolerance.

That's why I have recommended for years to "try it out". With FPGAs (but
not with ASICs) that is relatively easy, and you can be within a few
percentage points. You will see hardly any variation between speed
grades in this respect...

This is not a pretty story, but it might help when you understand the difficulties.
Peter Alfke, Xilinx Applications

 

[Peter Alfke]

Ralph Malph wrote:

No one said that Peter. The termal characteristics limit the power that
can be used in a given chip. So if you are sizing the power supply,
then this is a realistic number to go by. If a user wants to put a
higher power design in the FPGA, then it might even be a good idea for
the power supply to limit the power at the package level.

Keep in mind the purpose of the discussion, to size the power supply.

Still, if you say:
"The packages only tolerate a total power consumption of 20 W, so that
will be my power supply",
you either end up with an overly expensive power supply (in the 10-W case),
or with a power supply that shuts down the devices, since they need 25
or 30 W (in the other case).
You are not really any wiser. Maybe you are protected from burning up
the chips, but that is all.

Peter

 

[Ralph Malph]

Peter Alfke wrote:

Ralph Malph wrote:
No one said that Peter. The termal characteristics limit the power that
can be used in a given chip. So if you are sizing the power supply,
then this is a realistic number to go by. If a user wants to put a
higher power design in the FPGA, then it might even be a good idea for
the power supply to limit the power at the package level.

Keep in mind the purpose of the discussion, to size the power supply.

Still, if you say:
"The packages only tolerate a total power consumption of 20 W, so that
will be my power supply",
you either end up with an overly expensive power supply (in the 10-W case),
or with a power supply that shuts down the devices, since they need 25
or 30 W (in the other case).
You are not really any wiser. Maybe you are protected from burning up
the chips, but that is all.

That is one of the problems with Xilinx, they often seem to think that
there is only one type of customer who picks an app and designs the FPGA
like an ASIC. There are boards with FPGAs where you have no idea of
what range of applications will ultimately be done in the device. Think
reprogrammable! In those cases you can only design to the thermal limit
of the package.

No one is recommending that this is an optimal method of sizing a power
supply. It would be foolish for anyone to think that sizing a supply
this way was anything but a ceiling given no knowledge of the design.
And as someone else pointed out, there may be applications which run in
a pulsed mode where even this is not a ceiling. So it is always good to
know as much as possible about your FPGA design. But you don't always
know as much as you would like.

 

[glen herrmannsfeldt]

Peter Alfke wrote:

That posting suggested to deduce the max operating power backwards from
the package thermal resistance.
Do NOT do that !

Well, I thought that was what thermal resistance was for, though
it must be done right. You either need the thermal resistance
junction to air, or you need to add a heat sink and include the
thermal resistance to air for that heat sink. Then you need
the maximum junction temperature and the maximum air temperature.

Now, there is probably also an assumption that the heat generation
is uniform across the chip, and if that isn't true you would have
to correct for that.

I believe what you are saying is, if you don't know what you are
doing, don't do the calculation, and I agree with that...

(snip)

Most FPGAs these days can be melted down by a crazy (but legitimate)
design running at an outrageous ( but legitimate) clock frequency.
It's up to the user to keep the junction temperature within spec. All we
manufacturers can do is give you the best analysis tools we can come up with...

Has this changed over the years? I thought I asked it some
years ago, and got the opposite answer. Well, it might have
been for a more ordinary design, but at the highest clock rate
that it could run at.

OK, say for a synchronous design, all FF's have the same clock,
and 2CLB delay plus routing for the critical path. Signals
changing on the average every two clock cycles, and around
80% of CLB occupied. That is about what I had some years
ago, and may be a reasonably typical design.

-- glen

 

[erojr]

Peter Alfke wrote:

This is why power calculation is such a chore.

Agree.

On top of this, a 50% tolerance guess is no good.

In my _all_ recent designs the ¨real¨ FPGA on the board consumes much
less than calculated in advance. This means the on-board core voltage
converters on are all oversized - often more than 200%. No big problem,
but shows the difference between the design and reality.

I think the problem is to estimate the real occupancy, the ¨average
percent of Logic Cells toggling at each clock¨. This might strongly
depend on the input data.

That's why I have recommended for years to "try it out".

This means a prototype board with final FPGAs and realistic environment
- realistic input data included.

The funny side of the case is: when you finish to build and test a
prototype before designing the production version, already new FPGAs are
available. The new ones are cheaper and with HDL based design you can
port your design easily.

Just the power calculation and the prototype´s power measurement will
not be applicable ))

Janos Ero

 

[jim granville]

Ralph Malph wrote:

Peter Alfke wrote:

That posting suggested to deduce the max operating power backwards from
the package thermal resistance.
Do NOT do that !
Package choice is dominated by cost and price consideration, both on the
part of the chip manufacturer and on the part of the user.
To make the assumption "because it comes in this high thermal resistance
package, it will never dissipate more than x Watts" is, excuse the
word, silly.
Most FPGAs these days can be melted down by a crazy (but legitimate)
design running at an outrageous ( but legitimate) clock frequency.
It's up to the user to keep the junction temperature within spec. All we
manufacturers can do is give you the best analysis tools we can come up with...
Peter Alfke, Xilinx
=============================
Ralph Malph wrote:

But one way you can set a ceiling is to figure
out the maximum dissipation the package can provide and assume that can come from either of the two supplies. The may be very conservative, but
it will give you a *maximum*.



No one said that Peter. The termal characteristics limit the power that
can be used in a given chip. So if you are sizing the power supply,
then this is a realistic number to go by. If a user wants to put a
higher power design in the FPGA, then it might even be a good idea for
the power supply to limit the power at the package level.

Keep in mind the purpose of the discussion, to size the power supply.

I can see that it has some validity to use the device Power MAX, but
keep in mind that this is an AVERAGE value, and so can only give you the
AVERAGE power value ( and thus is mainly usefull for thermal budgeting
). It is possible to have burst operations that have much higher peak
currents, and the power supply should have the dynamic ability to
deliver that, even tho the average and thermal budget is lower.
There is also the FPGA startup, which can be an issue for power
supply budgets.

-jg

 

[Rene Tschaggelar]

Peter Alfke wrote:

Rene Tschaggelar wrote:

Thanks Peter,

the first sensible answer. What is wrong with a simple formula ?
Eg Imax = Io + 4mA/Mhz + I/O_load.

It'd help specifying the power supply as well as the heatsink.


Rene, unfortunately it is not that simple.
• Io is just the static leakage current, which tends to be
junction-temperature dependent, and unfortunately has increased
dramatically with 130 and 90 nm technology. Like a hundred times :-(
• mA per MHz depends on the frequency of each node, times the
capacitance of that node, and all this accumulated over the whole chip.
Some people (notably our friendly A competitor) make the tacit
assumption that everything behaves like a 16-bit counter, But that can
lead to very optimistic results, compared to a real DSP-like circuit
where everything is clocked at 300 MHz, and half the flip-flops and
interconnects change each clock period.
• I/O load is usually not static, but rather a load driving board- and
input capacitances. So you again need the capacitance and average
frequency of each pin.

This is why power calculation is such a chore.
On top of this, a 50% tolerance guess is no good. You don't want to
guardband your supply by a factor 2, and you definitely cannot be wrong
by a factor 2 when you calculate the junction over-temperature.
Theoretically, you have only between 50 (?) degrees max inside the box,
and 85 degrees at the junction. There is not much room to make a
mistake and accept an error or even a widetolerance.

That's why I have recommended for years to "try it out". With FPGAs (but
not with ASICs) that is relatively easy, and you can be within a few
percentage points. You will see hardly any variation between speed
grades in this respect...

This is not a pretty story, but it might help when you understand
the difficulties.

Thanks Peter,
I recognize that a lot of factors, some beyond control, influence the
current consumption. I'm in the low quantity market, where the design is
a major cost factor and the hardware cost is secondary. A must is
flexibility. Meaning that long after the prototype, when the stuff is in
production, the customer may have an additional wish which could be
fulfilled with the remaining 10 to 60% of the cells. Whatever it is,
it shouldn't be restricted by the power supply. I'd even be prepared
to have a four times stronger switcher already on the board. This
still comes cheaper than a new design. When the external power supply
needs to be stronger too, that shouldn't be a problem as the customer
provides for it.

I'm in the process of designing a new generic digital board that should
be useable for few years without yet having an idea about the applications.
Therefore I take a medium sized FPGA with 100k gates, the fastest version.
There is a lot more stuff on the board, but the FPGA may make up for the
most power consumption.

I'm having the impression that supplying chips which draw a lot of current
is considered loosing the face amongst the competitors. Nevertheless
if no one wants to burn the fingers, there could be competitions on
who can burn the most (or least current) in a specific chip while hinting
on the kind of applications at what clock rate.
I'm also aware that by fine tuning the design, one can trade speed against
size. So it is not only the chip that burns current, but also to a however
large degree the design.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[Vaughn Betz]

One last suggestion Rene -- if your design is already complete, you
can use the power calculation abilities of the Quartus simulator.
Since the simulator will compute the activity (switching rate) of each
node in your design, it will generally be more accurate than the
spreadsheet on the web, where you have to enter your guessed
activities. The actitivies calculated by the simulator are still only
as good as your test vectors -- if you have little idea of the typical
input vector usage patterns of your design, simulation may still help
some, but the accuracy will be less than ideal.

Of course, the simulator also knows the details of how many logic
cells, IOs, which standards, etc. are in your design. So you get the
right numbers there too.

But to use this you need a completed design with test vectors, and
simulation is also slower than doing what-if scenarios in a
spreadsheet.

To use the simulation-based power calculator from the GUI, go to
Assignments->Settings->Simulator, click on the Power Estimation
button, and check the "Estimate Power Consumption" box.
Then simulate your design. The design report file will now include a
power report section.

Regards,

Vaughn
Altera

 

[Rene Tschaggelar]

Vaughn Betz wrote:

One last suggestion Rene -- if your design is already complete, you
can use the power calculation abilities of the Quartus simulator.
Since the simulator will compute the activity (switching rate) of each
node in your design, it will generally be more accurate than the
spreadsheet on the web, where you have to enter your guessed
activities. The actitivies calculated by the simulator are still only
as good as your test vectors -- if you have little idea of the typical
input vector usage patterns of your design, simulation may still help
some, but the accuracy will be less than ideal.

Of course, the simulator also knows the details of how many logic
cells, IOs, which standards, etc. are in your design. So you get the
right numbers there too.

But to use this you need a completed design with test vectors, and
simulation is also slower than doing what-if scenarios in a
spreadsheet.

To use the simulation-based power calculator from the GUI, go to
Assignments->Settings->Simulator, click on the Power Estimation
button, and check the "Estimate Power Consumption" box.
Then simulate your design. The design report file will now include a
power report section.

Thanks Vaughn,
I saw the power calculator in Quartus. The project is nowhere yet.
I may have to do the Quartus design first then. Before the board.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net