Altera CPLD - Illegal assignment-global clock

[J.F. FOURCADIER]

Newbie

I try to use an Altera CPLD EPM7064. When I try to connect a register clock
input to a normal pin, I get the message "Illegal assignment-global
clock'input_clock' on pin 31.
I understand it's better to connect this kind of input on a dedicated clock
pin, but I cann't for wiring reasons.

The data sheet indicates a programmable register can be clocked by signals
from buried macrocells or I/O pins. How can I get this result ? I work on
the the graphic editor.

Thank you for your help !

Jean-François FOURCADIER, F4DAY

website : http://perso.wanadoo.fr/jf.fourcadier/

 

[Mike Treseler]

J.F. FOURCADIER wrote:

The data sheet indicates a programmable register can be clocked by signals
from buried macrocells or I/O pins. How can I get this result ? I work on
the the graphic editor.

On the 7064, the only route to the internal
clocks is through the special pins.

You may have to bend up a pin
and solder a wire.

-- Mike Treseler

 

[Dejan Durdenic]

You have probably checked "Automatic Global Clock" in the "Global Project
Logic Synthesis"
window - that will assign your clock to the global clock input pin.Uncheck
it, and you can route
your clock where you like (although there will be a speed penalty, of
course).

- Dejan

"J.F. FOURCADIER" <no_spam@wanadoo.fr> wrote in message
news:btcch9$ge6$1@news-reader4.wanadoo.fr...

Newbie

I try to use an Altera CPLD EPM7064. When I try to connect a register
clock
input to a normal pin, I get the message "Illegal assignment-global
clock'input_clock' on pin 31.
I understand it's better to connect this kind of input on a dedicated
clock
pin, but I cann't for wiring reasons.

The data sheet indicates a programmable register can be clocked by signals
from buried macrocells or I/O pins. How can I get this result ? I work on
the the graphic editor.

Thank you for your help !

Jean-François FOURCADIER, F4DAY

website : http://perso.wanadoo.fr/jf.fourcadier/