Altera configuration Problem?? Help

[ndesi]

Hello

I have board with Altera stratix FPGA. Because of board
design mistake, MSEL[2:0] pins are always logic 1. I can not cut
or modify because tarce are not visible (burried).

Can i use this board? if yes what configurtaion i should use.
can i use JTAG configuration?

Thanks

 

[Steve]

ndesi wrote:

Hello

I have board with Altera stratix FPGA. Because of board
design mistake, MSEL[2:0] pins are always logic 1. I can not cut
or modify because tarce are not visible (burried).

Can i use this board? if yes what configurtaion i should use.
can i use JTAG configuration?

Thanks

Well you didn't tell us what sort of configuration method you were intending
to use and/or what configuration options exist (or not) on your board.
Forgive me if I can't help there. I suggest RTFineM.

Seriously, I will make a hopefully more useful comment. Have you considered
drilling a well placed hole or two in your board to remove the undesired
internal traces? I've used this method to deal with buried PCB mistakes.
Even re-ground a drill bit to make a flat bottomed hole. A milling machine,
to precisely guide the cut is ideal. Other times, a hole straight through
the board can be done with a hand drill. Sometimes you have take a few
steps backward and create more damage, but a few mod wires may be able to
fix the new damage and original problem.

Good Luck, Steve