P
Pino
Guest
To all,
I've discovered that there is some significant propagation delay
between the input and bidirectional pin & bidirectional pin to output
pin in my simulation. I've compared the function LPM_BUSTRI within
Quartus, a construction made up from Tri-state buffers within Quartus
both within a BDF graph and also made my own configuration developed
using VHDL. They all work similarily but the concern is the
propagation delay which seems to be large (~ 7-10 ns). This limits
the total operation of the chip that I have to 100 MHz, which is a bit
strange? The chipset to which I synthesized too in Quartus is
EP1S10F780C6ES.
Can anyone tell me if this propagation delay is EXPECTED??? If so,
what is causing this FPGA speed limit? Can I reduce this somehow? I
anticipate to use this with my memory controller for PC100 SDRAM.
The configuration coded is as follows:
(not)OE
|
|
|\
| \
IN -------| /-------
|/ |
|----------Bidi-pin
/| |
OUT -------/ |-------
\ |
\|
|
|
OE
The functional VHDL code that I have implemented and simulated is as
follows:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Tristate_Buffer IS
PORT
(
OE : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC;
BUS_INOUT : INOUT STD_LOGIC
);
END Tristate_Buffer;
ARCHITECTURE mainRTL OF Tristate_Buffer IS
signal bus_wire1, bus_wire2 :STD_LOGIC;
BEGIN
op_assign_process: PROCESS (OE, DATA_IN, BUS_INOUT)
BEGIN
IF OE = '1' THEN
bus_wire1 <= DATA_IN;
bus_wire2 <= 'Z';
ELSE
bus_wire1 <= 'Z';
bus_wire2 <= BUS_INOUT;
END IF;
DATA_OUT <= bus_wire2;
END PROCESS op_assign_process;
bus_assign_process: PROCESS (bus_wire1)
BEGIN
BUS_INOUT <= bus_wire1;
END PROCESS bus_assign_process;
END mainRTL;
I've discovered that there is some significant propagation delay
between the input and bidirectional pin & bidirectional pin to output
pin in my simulation. I've compared the function LPM_BUSTRI within
Quartus, a construction made up from Tri-state buffers within Quartus
both within a BDF graph and also made my own configuration developed
using VHDL. They all work similarily but the concern is the
propagation delay which seems to be large (~ 7-10 ns). This limits
the total operation of the chip that I have to 100 MHz, which is a bit
strange? The chipset to which I synthesized too in Quartus is
EP1S10F780C6ES.
Can anyone tell me if this propagation delay is EXPECTED??? If so,
what is causing this FPGA speed limit? Can I reduce this somehow? I
anticipate to use this with my memory controller for PC100 SDRAM.
The configuration coded is as follows:
(not)OE
|
|
|\
| \
IN -------| /-------
|/ |
|----------Bidi-pin
/| |
OUT -------/ |-------
\ |
\|
|
|
OE
The functional VHDL code that I have implemented and simulated is as
follows:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY Tristate_Buffer IS
PORT
(
OE : IN STD_LOGIC;
DATA_IN : IN STD_LOGIC;
DATA_OUT : OUT STD_LOGIC;
BUS_INOUT : INOUT STD_LOGIC
);
END Tristate_Buffer;
ARCHITECTURE mainRTL OF Tristate_Buffer IS
signal bus_wire1, bus_wire2 :STD_LOGIC;
BEGIN
op_assign_process: PROCESS (OE, DATA_IN, BUS_INOUT)
BEGIN
IF OE = '1' THEN
bus_wire1 <= DATA_IN;
bus_wire2 <= 'Z';
ELSE
bus_wire1 <= 'Z';
bus_wire2 <= BUS_INOUT;
END IF;
DATA_OUT <= bus_wire2;
END PROCESS op_assign_process;
bus_assign_process: PROCESS (bus_wire1)
BEGIN
BUS_INOUT <= bus_wire1;
END PROCESS bus_assign_process;
END mainRTL;