Altera Avalon Bus Signal Monitoring?

[Pino]

To all,

I have created a Master peripheral and use SOPC builder to connect
to an SDRAM controller contained within the library provided for the
1s10 NIOS development kit. When I developed my Master peripheral, I
had used the Avalon Bus Specification manual and developed a state
machine that uses the signals required to interface with the Avalon
Bus (ie. WaitRequest, Read_N, readdata, readdatavalid etc...). The
Master peripheral state machine allows for either a READ or a WRITE.
However, I have noticed that no data is either written too or read
from the Avalon Bus (a.k.a. to the SDRAM). I have put some
additional ports, to trace the state machine states and I do verify
that I am cycling through the states correctly until the state
machine gets stuck in a given state. The LOC_POINTER output port
allows me to verify the state machine's current state condition. The
reason for my code being stuck is that my transition back to an IDLE
state depends on the Avalon Bus signals (ie readdatavalid or
waitrequest). If these don't change then I remain in the same state.
Furthermore when I validate this using the development board, the
values returned on the READ phase seems to always be a HIGH,
eventhough I am provisioning the contents of the memory with some
other value. It is apparent that this code is not working in either
WRITE or READ.

Does someone know who to probe within the SOPC environment what these
signals are? I want to ensure that the signals are at least getting
to the Avalon Bus interface. Any other suggestions on what I'm not
understanding with regards to the Avalon Bus?


For your reference, here's a copy of my Master Peripheral code (state
machine) in VHDL which I hope does not contain any invalid errors
based on my understanding of the Avalon Interface:


ENTITY Master_Memory_RW IS
PORT(
CLK : IN STD_LOGIC;
RESET : IN STD_LOGIC; -- Reset state machine
RW_CTL : IN STD_LOGIC; -- Read = 1, & Write = 0
ACTION : IN STD_LOGIC; -- State machine status variable (1 = go to
read/write, 0 = do nothing)
WAITREQUEST : IN STD_LOGIC; -- Allows Master to wait until data is
available from Avalon Bus
READDATAVALID : IN STD_LOGIC; -- To handle cases of latency for Read
transfers from Avalon Bus; This will allow Master to perform other
tasks while waiting for read data.
INP_ADDR : IN STD_LOGIC_VECTOR (11 DOWNTO 0); -- User Input
Address INP_BA : IN STD_LOGIC_VECTOR (1 DOWNTO 0); -- User Input
Bank
INP_DATA : IN STD_LOGIC_VECTOR (2 DOWNTO 0); -- User Input Data
READ_DATA : IN STD_LOGIC_VECTOR (31 DOWNTO 0); -- Input data line
BYTEENABLE_N : OUT STD_LOGIC_VECTOR (3 DOWNTO 0);
WRITE_DATA : OUT STD_LOGIC_VECTOR (31 DOWNTO 0); -- Output data
line
EXT_WRITE_DATA : OUT STD_LOGIC_VECTOR (2 DOWNTO 0); -- Output data
line
EXT_MEM_ADDR : OUT STD_LOGIC_VECTOR (11 DOWNTO 0); -- Memory address
sent to Avalon Bus
EXT_BA : OUT STD_LOGIC_VECTOR (1 DOWNTO 0); -- Bank Address to be
used with Byte Enable line for Avalon Bus
EXT_WRITE_N : OUT STD_LOGIC; -- Write enable bit to the Avalon Bus
EXT_READ_N : OUT STD_LOGIC; -- Write enable bit to the Avalon Bus
LOC_POINTER : OUT STD_LOGIC_VECTOR (3 DOWNTO 0)
);

END ENTITY Master_Memory_RW;

-- Architecture Body
ARCHITECTURE main_rtl OF Master_Memory_RW IS

-- State Machine Definitions
TYPE EXCHANGE_STATE IS (INIT, IDLE, READ, WRITE, DATA_CAPTURE);
SIGNAL state, nextstate :EXCHANGE_STATE;

BEGIN

state_register: PROCESS (CLK, RESET)
BEGIN
IF (RESET = '1') THEN
state <= INIT;
ELSIF (CLK'EVENT AND CLK = '1') THEN
state <= nextstate;
END IF;
END PROCESS state_register;

rw_control: PROCESS (state)
BEGIN
CASE state IS
WHEN INIT =>

BYTEENABLE_N <= "1111";
WRITE_DATA <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
EXT_WRITE_DATA <= "ZZZ";
EXT_MEM_ADDR <= "ZZZZZZZZZZZZ";
EXT_BA <= "ZZ";
EXT_WRITE_N <= 'Z';
EXT_READ_N <= 'Z';
LOC_POINTER <= "0000";

nextstate <= IDLE;


WHEN IDLE =>

BYTEENABLE_N <= "1111";
WRITE_DATA <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
EXT_WRITE_DATA <= "ZZZ";
EXT_MEM_ADDR <= "ZZZZZZZZZZZZ";
EXT_BA <= "ZZ";
EXT_WRITE_N <= 'Z';
EXT_READ_N <= 'Z';

-- User action to either perform a READ/WRITE operation
IF ACTION = '1' THEN
LOC_POINTER <= "0010";
IF RW_CTL = '1' THEN
nextstate <= READ;
ELSE
nextstate <= WRITE;
END IF;
ELSE
LOC_POINTER <= "0001";
nextstate <= IDLE;
END IF;

WHEN READ =>

BYTEENABLE_N <= "0000";
EXT_MEM_ADDR <= INP_ADDR;
EXT_BA <= INP_BA;
WRITE_DATA <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
EXT_WRITE_DATA <= "ZZZ";


EXT_WRITE_N <= '1';
EXT_READ_N <= '0';

-- Validate if Avalon Bus has issued a WAIT state
-- Capture Data from Bus only when WaitRequest is
-- deasserted.
IF WAITREQUEST = '1' THEN
nextstate <= READ;
ELSE
nextstate <= DATA_CAPTURE;
END IF;
LOC_POINTER <= "0011";

WHEN WRITE =>

BYTEENABLE_N <= "0000";
WRITE_DATA <= "00000000000000000000000000000" & INP_DATA(2 DOWNTO
0);
EXT_MEM_ADDR <= INP_ADDR;
EXT_BA <= INP_BA;
EXT_WRITE_DATA <= "ZZZ";


EXT_WRITE_N <= '0';
EXT_READ_N <= '1';

IF WAITREQUEST = '0' THEN
nextstate <= WRITE;
ELSE
nextstate <= IDLE;
END IF;

LOC_POINTER <= "0100";


WHEN DATA_CAPTURE =>

BYTEENABLE_N <= "0000";
EXT_MEM_ADDR <= INP_ADDR;
EXT_BA <= INP_BA;
WRITE_DATA <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";

EXT_WRITE_N <= '1';
EXT_READ_N <= '0';

IF READDATAVALID = '0' THEN
EXT_WRITE_DATA <= READ_DATA(2 DOWNTO 0);
nextstate <= DATA_CAPTURE;
ELSE
EXT_WRITE_DATA <= READ_DATA(2 DOWNTO 0);
--EXT_WRITE_DATA <= "ZZZ";
nextstate <= IDLE;
END IF;
LOC_POINTER <= "0101";

END CASE;
END PROCESS rw_control;

END ARCHITECTURE main_rtl;