Y
yaser fathy
Guest
Hello,
I'm learning an opensource cad tool called alliance , it takes a vhdl
design and turns it into a wafer digital layout , its VHDL compiler is
called SYF , the problem is that a code that compiled successfully on
modelsim won't compile here , my VHDL is not very strong so I hope
someone could give my an explanation :
the problem is with variable declaration
process(CS,wordin,reset)
variable addr : std_logic_vector (7 DOWNTO 0);
begin
....
error : ILLEGAL DECLARATION
at the variable declaration line
any help ?
I'm learning an opensource cad tool called alliance , it takes a vhdl
design and turns it into a wafer digital layout , its VHDL compiler is
called SYF , the problem is that a code that compiled successfully on
modelsim won't compile here , my VHDL is not very strong so I hope
someone could give my an explanation :
the problem is with variable declaration
process(CS,wordin,reset)
variable addr : std_logic_vector (7 DOWNTO 0);
begin
....
error : ILLEGAL DECLARATION
at the variable declaration line
any help ?