All Paths in RTL Module

H

HDLDesigner

Guest
Hello,

I have a RTL logic from which I want to know all the paths from
input to output. I tried synthesis tools, but not getting all the
paths. Can anybody sugessest any method to find all the paths from
input to output in a RTL.

Thanks.
 
this should be possible using synthesis tools which <tool,command> did
you use?
Regards
Jahagirdar Vijayvithal S

* HDLDesigner <hdl_designer@rediffmail.com>:
Hello,

I have a RTL logic from which I want to know all the paths from
input to output. I tried synthesis tools, but not getting all the
paths. Can anybody sugessest any method to find all the paths from
input to output in a RTL.

Thanks.
Click to expand...
 
Hello Jahagirdar Vijayvithal ,

I tried with general ASIC synthesis tools like Synopsys DC Shell and
Cadence BuildGates. But could not find suitable command to see All
(not only the critical paths) the paths from chip input to output s
listed. Also Debussy tool gives driver and sink for signals (all,
including the internal). Still this is not suitable for extracting the
information that I want. The information generated through Debussy for
load and driver are for a single intermediate combo logic, not crosses
the sequencial element boundary.

Any particular command in DC or BuildGates can you point out for this
?

Regards

Jahagirdar Vijayvithal S <FILTERjvsSPAM@india.ti.com> wrote in message news:<bvnm03$re7$1@home.itg.ti.com>...
this should be possible using synthesis tools which <tool,command> did
you use?
Regards
Jahagirdar Vijayvithal S

* HDLDesigner <hdl_designer@rediffmail.com>:
Hello,

I have a RTL logic from which I want to know all the paths from
input to output. I tried synthesis tools, but not getting all the
paths. Can anybody sugessest any method to find all the paths from
input to output in a RTL.

Thanks.
Click to expand...
 
"HDLDesigner" <hdl_designer@rediffmail.com> wrote in message
news:1f923b28.0402040254.7aebf98f@posting.google.com...

I tried with general ASIC synthesis tools like Synopsys DC Shell and
Cadence BuildGates. But could not find suitable command to see All
(not only the critical paths) the paths from chip input to output s
listed. Also Debussy tool gives driver and sink for signals (all,
including the internal). Still this is not suitable for extracting the
information that I want. The information generated through Debussy for
load and driver are for a single intermediate combo logic, not crosses
the sequencial element boundary.
Click to expand...
On our website www.doulos.com/knowhow/tcltk you will find a Tcl
script that will locate the driver(s) of any signal in a synthesised
design, if you are using dc_shell-t (Tcl mode for DC). You could
easily extend this to start from an output, find its driver,
find all inputs of that driver, find those inputs' drivers, and
so on. You would need to keep a log of all cells you have
visited, so that you can ignore already-visited cells as you
traverse the paths, but this is easy enough in Tcl.

Alternatively, read the Synopsys man page for the get_timing_paths
command and look at the -nworst option; set this to a really, really
large number so that you get to see all the paths.

Whichever method you choose, it will give DC a lot of work to do.
Start it running, then go away and make yourself a nice cup of tea
while you wait for it to finish, then go away and have a short
holiday while you still wait for it to finish.

Are you SURE you really want to do this? I think you will
generate a terrifyingly large amount of information for
any reasonable-size design...
--

Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * Perl * Tcl/Tk * Verification * Project Services

Doulos Ltd. Church Hatch, 22 Market Place, Ringwood, Hampshire, BH24 1AW, UK
Tel: +44 (0)1425 471223 mail: jonathan.bromley@doulos.com
Fax: +44 (0)1425 471573 Web: http://www.doulos.com

The contents of this message may contain personal views which
are not the views of Doulos Ltd., unless specifically stated.
 
You can use the Undertow Suite for doing exactly this. This software
is ideal even if your design is huge, since it will, construct your
schematic on the fly almost instantly provided your design is
hierarchical. The schematic will be an exact rendition of your RTL
code. This tool has been tested extensively on 10 million+ gate
equivalent designs and even on designs of this size it is extremely
fast. If you have very large waveform files for the simulation of your
design, these will also load almost instantly so that these signal
values can be annotated right on your schematic, for the current
position of the T0 cursor. You can down load the latest Undertow Suite
at www.veritools.com, or www.veritools-web.com

Robert Schopmeyer/Veritools, Inc.

thhdl_designer@rediffmail.com (HDLDesigner) wrote in message news:<1f923b28.0402040254.7aebf98f@posting.google.com>...
Hello Jahagirdar Vijayvithal ,

I tried with general ASIC synthesis tools like Synopsys DC Shell and
Cadence BuildGates. But could not find suitable command to see All
(not only the critical paths) the paths from chip input to output s
listed. Also Debussy tool gives driver and sink for signals (all,
including the internal). Still this is not suitable for extracting the
information that I want. The information generated through Debussy for
load and driver are for a single intermediate combo logic, not crosses
the sequencial element boundary.

Any particular command in DC or BuildGates can you point out for this
?

Regards

Jahagirdar Vijayvithal S <FILTERjvsSPAM@india.ti.com> wrote in message news:<bvnm03$re7$1@home.itg.ti.com>...
this should be possible using synthesis tools which <tool,command> did
you use?
Regards
Jahagirdar Vijayvithal S

* HDLDesigner <hdl_designer@rediffmail.com>:
Hello,

I have a RTL logic from which I want to know all the paths from
input to output. I tried synthesis tools, but not getting all the
paths. Can anybody sugessest any method to find all the paths from
input to output in a RTL.

Thanks.
Click to expand...
 
hdl_designer@rediffmail.com (HDLDesigner) wrote in message news:<1f923b28.0401310200.3f702b10@posting.google.com>...
Hello,

I have a RTL logic from which I want to know all the paths from
input to output. I tried synthesis tools, but not getting all the
paths. Can anybody sugessest any method to find all the paths from
input to output in a RTL.

Thanks.
Click to expand...
"async_path_report" procedure returns report of all input->output
paths:


# Converts DC collection to TCL list
#-----------------------------------
proc c2l {collection} {
set my_list {}
foreach_in_collection coll_element $collection {
set element [get_object_name $coll_element]
lappend my_list $element
}
return $my_list
}


# Generates Asynchronous path report (Input ports - to Output ports)
#====================================================================
proc async_path_report {} {
puts "\n\n ASYNCRONOUS PATHS REPORT"
puts "|------------------------------------------------------------------|"
puts [format "%-25s %-40s %-1s" "| FROM INPUT" "| TO OUTPUT" "|"]
puts [format "%-25s %-40s %-1s" "| ==========" "| =========" "|"]
puts "|-------------------------|----------------------------------------|"

foreach_in_collection input [all_inputs] {
set conn_ports [get_ports [c2l [all_fanout -from [get_object_name
$input] -endpoints_only]] \
-filter "@port_direction == out"]
if {[sizeof_collection $conn_ports] > 0} {
set in [get_object_name $input]
set out_ports [c2l $conn_ports]

puts [format "%-25s %-40s %-1s" "| $in" "| [lindex $out_ports
0]" "|"]
for {set i 1} {$i < [llength $out_ports]} {incr i} {
puts [format "%-25s %-40s %-1s" "|" "| [lindex $out_ports $i]"
"|"]
}
puts "|-------------------------|----------------------------------------|"

}
}
}

Regards,
Alexander Gnusin
 
Use pearl the static timing tool from cadence or synopsys' version of the
same thing.

"HDLDesigner" <hdl_designer@rediffmail.com> wrote in message
news:1f923b28.0401310200.3f702b10@posting.google.com...
Hello,

I have a RTL logic from which I want to know all the paths from
input to output. I tried synthesis tools, but not getting all the
paths. Can anybody sugessest any method to find all the paths from
input to output in a RTL.

Thanks.
Click to expand...
 
You must log in or register to reply here.

Welcome to EDABoard.com

Sponsor

Back
Top