All in a single clk cycle

[RSGUPTA]

Hi I have a requirement to be implemented in a single cycle in
Verilog.
Requirement:
Wrap_Boundary = (INT(Start_Address / (Number_Bytes x Burst_Length)))
x
(Number_Bytes x Burst_Length).
Where,
• Start_Address = ADDR
• Number_Bytes = 2**SIZE
• Burst_Length = LEN + 1

SIZE is 3 bit register and LEN is 4 bit register and the length of the
burst must be 2, 4, 8, or 16.
ADDR is fixed to be 32 bits.

Please can someone let me know how to implement in a single clk cycle.

Thanks ...