All Digital PLL

[Ehsan]

Hey Folks,

I am trying to implemented an all digital PLL on Xilinx FPGAs. First,
I wrote some Matlab code to see the functionality of the PLL.
Everything seemed to work fine. Then I quantized the operations in
Matlab to find out the amount of precision I need in hardware. That's
when the PLL stopped working, or started oscillating! It seems to me
that every part of the PLL is OK with fixed precession, i.e. 20 bits,
except for the Loop Filter which needs to be double-precession. One
reason can be the fact that Loop Filter coefficients are very small
numbers so their effect is not preserved in finite precession. Since
my target is FPGA, I don't have any idea how to implement double-
precession function. Or, is it even possible? I wondered if any of you
has any kind of experience with digital PLLs or double precession
operations in FPGAs.

Thank you!

 

[Tim Wescott]

On 07/27/2010 09:38 AM, Ehsan wrote:

Hey Folks,

I am trying to implemented an all digital PLL on Xilinx FPGAs. First,
I wrote some Matlab code to see the functionality of the PLL.
Everything seemed to work fine. Then I quantized the operations in
Matlab to find out the amount of precision I need in hardware. That's
when the PLL stopped working, or started oscillating! It seems to me
that every part of the PLL is OK with fixed precession, i.e. 20 bits,
except for the Loop Filter which needs to be double-precession. One
reason can be the fact that Loop Filter coefficients are very small
numbers so their effect is not preserved in finite precession. Since
my target is FPGA, I don't have any idea how to implement double-
precession function. Or, is it even possible? I wondered if any of you
has any kind of experience with digital PLLs or double precession
operations in FPGAs.

I assume you mean double-precision floating point when you say
"double-precession"? It's not necessary. One generally needs more
precision in the loop filter (specifically in the integrator in the loop
filter) than one does anywhere else, but one can still keep things as
fixed-point numbers.

Nearly everyone I know who's implemented a digital PLL knows in their
heart that there's only one unique kind; which one of the many unique
kinds of digital PLL there are seems to depend on what industry you're
from, or even what company you've worked for.

So tell us more about the one unique kind of digital PLL architecture
that you're working on and we may be able to help.

What are you trying to achieve? Frequency synthesis? Lock an
oscillator (or motor) to an external source? Synchronize to a carrier
in a communications system? Are you trying to stabilize a noisy
oscillator to a stable reference, or are you trying to smooth out the
phase and frequency of a noisy reference while preserving the underlying
DC behavior?

What are you using for an oscillator? A 'traditional'
phase-incrementing NCO? A counter with a varying target or load value?
An external XCO driven by a DAC? A motor driven by a DAC?

What are you using for a phase detector?

What are you using for a loop filter? Just a PI filter? PI filter +
low pass? Something fancy?

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

 

[dbd]

On Jul 27, 9:38 am, Ehsan <ehsan.hosse...@gmail.com> wrote:

Hey Folks,

I am trying to implemented an all digital PLL ...

Thank you!

You might take a look at the discussion of precision and bit alignment
here:

http://www.compdsp.com/presentations/Jacobsen/abineau_dpll_analysis.pdf

Dale B. Dalrymple

 

[Ehsan]

On Jul 27, 11:57 am, Tim Wescott <t...@seemywebsite.com> wrote:

On 07/27/2010 09:38 AM, Ehsan wrote:


I assume you mean double-precision floating point when you say
"double-precession"?  It's not necessary.  One generally needs more
precision in the loop filter (specifically in the integrator in the loop
filter) than one does anywhere else, but one can still keep things as
fixed-point numbers.

Nearly everyone I know who's implemented a digital PLL knows in their
heart that there's only one unique kind; which one of the many unique
kinds of digital PLL there are seems to depend on what industry you're
from, or even what company you've worked for.

So tell us more about the one unique kind of digital PLL architecture
that you're working on and we may be able to help.

What are you trying to achieve?  Frequency synthesis?  Lock an
oscillator (or motor) to an external source?  Synchronize to a carrier
in a communications system?  Are you trying to stabilize a noisy
oscillator to a stable reference, or are you trying to smooth out the
phase and frequency of a noisy reference while preserving the underlying
DC behavior?

What are you using for an oscillator?  A 'traditional'
phase-incrementing NCO?  A counter with a varying target or load value?
  An external XCO driven by a DAC?  A motor driven by a DAC?

What are you using for a phase detector?

What are you using for a loop filter?  Just a PI filter?  PI filter +
low pass?  Something fancy?

--

Tim Wescott
Wescott Design Serviceshttp://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details athttp://www.wescottdesign.com/actfes/actfes.html

Thank you Tim. I'm trying to use the PLL for timing synchronization in
a communication receiver. The Loop filter is simply a PI filter with
two coefficients, i.e. C1 and C2. I can write the filter equation for
you:

y[n] = C1*x[n] + (C2-C1)*x[n-1] + y[n-1]

For the phase detector, I am using an Early/Late error detector which
simply uses the time difference of two adjacent samples to generate
error signal.
The VCO is a counter which is decremented according to the output of
the loop filter.

I hope this could help you to have a picture of my PLL in your
mind.

 

[Tim Wescott]

On 07/27/2010 12:39 PM, Ehsan wrote:

On Jul 27, 11:57 am, Tim Wescott<t...@seemywebsite.com> wrote:
On 07/27/2010 09:38 AM, Ehsan wrote:


I assume you mean double-precision floating point when you say
"double-precession"? It's not necessary. One generally needs more
precision in the loop filter (specifically in the integrator in the loop
filter) than one does anywhere else, but one can still keep things as
fixed-point numbers.

Nearly everyone I know who's implemented a digital PLL knows in their
heart that there's only one unique kind; which one of the many unique
kinds of digital PLL there are seems to depend on what industry you're
from, or even what company you've worked for.

So tell us more about the one unique kind of digital PLL architecture
that you're working on and we may be able to help.

What are you trying to achieve? Frequency synthesis? Lock an
oscillator (or motor) to an external source? Synchronize to a carrier
in a communications system? Are you trying to stabilize a noisy
oscillator to a stable reference, or are you trying to smooth out the
phase and frequency of a noisy reference while preserving the underlying
DC behavior?

What are you using for an oscillator? A 'traditional'
phase-incrementing NCO? A counter with a varying target or load value?
An external XCO driven by a DAC? A motor driven by a DAC?

What are you using for a phase detector?

What are you using for a loop filter? Just a PI filter? PI filter +
low pass? Something fancy?

--

Tim Wescott
Wescott Design Serviceshttp://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details athttp://www.wescottdesign.com/actfes/actfes.html


Thank you Tim. I'm trying to use the PLL for timing synchronization in
a communication receiver. The Loop filter is simply a PI filter with
two coefficients, i.e. C1 and C2. I can write the filter equation for
you:

y[n] = C1*x[n] + (C2-C1)*x[n-1] + y[n-1]

For the phase detector, I am using an Early/Late error detector which
simply uses the time difference of two adjacent samples to generate
error signal.
The VCO is a counter which is decremented according to the output of
the loop filter.

I hope this could help you to have a picture of my PLL in your
mind.

If I'm getting my math right your loop filter is equivalent to

u[n] = u[n-1] + C2 * x[n],
y[n] = u[n] + (C1-C2) * x[n].

This not only has the advantage of not requiring you to store prior
values of the input, it should also let you separate the math around the
integrator state (u) which will need to be fairly high precision from
the proportional section.

Figure that u[n] needs to resolve the smallest value in x[n] times C2,
and that C2 will be several powers of two smaller than 1, most likely --
certainly it'll be several powers of two smaller than C1.

--

Tim Wescott
Wescott Design Services
http://www.wescottdesign.com

Do you need to implement control loops in software?
"Applied Control Theory for Embedded Systems" was written for you.
See details at http://www.wescottdesign.com/actfes/actfes.html

 

[-jg]

On Jul 28, 7:39 am, Ehsan <ehsan.hosse...@gmail.com> wrote:

The VCO is a counter which is decremented according to the output of
the loop filter.

Err, a Counter is not a VCO ?
This will give you a choice of quantized frequency outputs, and the
control loop will need to choose a weighted ratio, that averages to
your desired frequency.

Is the quantize and jitter tolerable in your application ?



-jg