Aligning process outputs with pipeline delays

[DW]

Hello,
I have 2 verilog modules (say A and B) clocked by a common clock and the
pipeline delay through each is known but could change (as the design
progresses) and either one could be greater than or equal to the other. The
outputs from the modules are to be combined in some way so the outputs must
be aligned in time. (I have in fact used pre-processor defines to define
the delays in .h files e.g. A.h and B.h for the calling module).
My problem is that I need to insert a pipeline delay on the output of A or B
(or perhaps neither) to align the outputs but the pipeline delay could be on
the output of A *or* B *or* neither depending on the actual delays.
What is the neatest and best way to do this? I don't want to hard code
something which may break if (more likely "when") the internal delays of A
and B change.
Should I use the pre-processor or is there another way - could the
"generate" feature be of any use?

Your help would be very much appreciated.

 

[Jim Wu]

Should I use the pre-processor or is there another way - could the
"generate" feature be of any use?

"generate" should work for you if you simulation/synthesis tools support
some of the verilog-2001 features. e.g

// assume minimum 1 stage pipeline
always @ (posedge clk)
out[OUT_WIDTH-1:0] <= in;

generate for (i = 1; i < PIPELINE_STAGES; i = i + 1) begin : pipeline
always @ (posedge clk)
out[(i+1)*OUT_WIDTH-1 -:OUT_WIDTH] <=
out[i*OUT_WIDTH-1 -:OUT_WIDTH];
end
endgenerate

assign out_fianl = out[PIPELINE_STAGES*OUT_WIDTH-1 -:OUT_WIDTH] ;

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips

 

The for-generate may not give you anything you couldn't
already get by using an ordinary for-loop and an array
inside an ordinary always block (assuming that your
synthesis tool is capable of generating a pipeline for
that). For example,

always @(posedge clk) begin
pipe[0] <= in;
for (i = 1; i < STAGES; i = i + 1)
pipe <= pipe[i-1];
end

It might be a bit awkward to get zero stages that way,
but I suppose you could handle it in the final output
with something like

assign out = (STAGES == 0) ? in : pipe[STAGES-1];

With zero stages, the value of out would be connected
directly to in, for no delay. The synthesis tool would
presumably recognize that the one stage of pipe was
not being used, and throw it away.

Or you could use a conditional generate to instantiate
different logic for the zero-stage case.

 

[Jim Wu]

So in this case you have already defined a variable:
reg [ (PIPELINE_STAGES+1)*OUT_WIDTH-1 : 0 ] out;

For some strange reason, I always try to avoid using two dimensional "reg"
arrays for regular registers (i.e. non-memory). After reading Steve's
message, I tried a small test case with two-dimensional arrays and my
synthesis tools worked just fine. In other words, you can try define

reg [OUT_WIDTH-1:0] out[PIPELINE_STAGES-1:0];

which is much cleaner.

This assumes (as you have pointed out) that there is a minimum pipeline
delay of 1 but I wonder if it could be arranged so a minimum pipeline
delay
of 0 could be defined. I will have to think about this. Thanks for you
reply.

A conditional generate statement would probably work.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips

 

[DW]

"Jim Wu" <nospam@nospam.com> wrote in message
news:cv28ep$bn11@cliff.xsj.xilinx.com...

Should I use the pre-processor or is there another way - could the
"generate" feature be of any use?


"generate" should work for you if you simulation/synthesis tools support
some of the verilog-2001 features. e.g

// assume minimum 1 stage pipeline
always @ (posedge clk)
out[OUT_WIDTH-1:0] <= in;

generate for (i = 1; i < PIPELINE_STAGES; i = i + 1) begin : pipeline
always @ (posedge clk)
out[(i+1)*OUT_WIDTH-1 -:OUT_WIDTH] <=
out[i*OUT_WIDTH-1 -:OUT_WIDTH];
end
endgenerate

assign out_fianl = out[PIPELINE_STAGES*OUT_WIDTH-1 -:OUT_WIDTH] ;

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips


So in this case you have already defined a variable:

reg [ (PIPELINE_STAGES+1)*OUT_WIDTH-1 : 0 ] out;

This assumes (as you have pointed out) that there is a minimum pipeline
delay of 1 but I wonder if it could be arranged so a minimum pipeline delay
of 0 could be defined. I will have to think about this. Thanks for you
reply.

 

[Jason Zheng]

DW wrote:

Hello,
I have 2 verilog modules (say A and B) clocked by a common clock and the
pipeline delay through each is known but could change (as the design
progresses) and either one could be greater than or equal to the other. The
outputs from the modules are to be combined in some way so the outputs must
be aligned in time. (I have in fact used pre-processor defines to define
the delays in .h files e.g. A.h and B.h for the calling module).
My problem is that I need to insert a pipeline delay on the output of A or B
(or perhaps neither) to align the outputs but the pipeline delay could be on
the output of A *or* B *or* neither depending on the actual delays.
What is the neatest and best way to do this? I don't want to hard code
something which may break if (more likely "when") the internal delays of A
and B change.
Should I use the pre-processor or is there another way - could the
"generate" feature be of any use?

Your help would be very much appreciated.


You could easily write a python script to accomplish that goal, here's

the steps you need to take:

1. grep A.h and B.h to figure out how much delay you need to put on
either A or B
2. generate delay path by printing to standard out or to a pre-defined
top-level module.

-jz

 

[DW]

<sharp@cadence.com> wrote in message
news:1108669200.796619.285140@f14g2000cwb.googlegroups.com...

The for-generate may not give you anything you couldn't
already get by using an ordinary for-loop and an array
inside an ordinary always block (assuming that your
synthesis tool is capable of generating a pipeline for
that). For example,

always @(posedge clk) begin
pipe[0] <= in;
for (i = 1; i < STAGES; i = i + 1)
pipe <= pipe[i-1];
end

It might be a bit awkward to get zero stages that way,
but I suppose you could handle it in the final output
with something like

assign out = (STAGES == 0) ? in : pipe[STAGES-1];

With zero stages, the value of out would be connected
directly to in, for no delay. The synthesis tool would
presumably recognize that the one stage of pipe was
not being used, and throw it away.

Or you could use a conditional generate to instantiate
different logic for the zero-stage case.

I already have a pipeline module written in exactly this way (the width and

depth of the pipe are parameters). I intend to use that to provide the
pipeline delay required in my original example. It may be better if I get
the pipeline to handle this internally, so if the depth parameter (defined
ultimately by a `define) is <= 0, the module would simply implement a piece
of wire. I think this would be the most elegant way of dealing with it.
Referring to my original example, both A and B would have a pipeline
instance connected on the output

Thanks (again).

 

[DW]

"Jim Wu" <nospam@nospam.com> wrote in message
news:cv385r$rcd1@cliff.xsj.xilinx.com...

So in this case you have already defined a variable:
reg [ (PIPELINE_STAGES+1)*OUT_WIDTH-1 : 0 ] out;


For some strange reason, I always try to avoid using two dimensional "reg"
arrays for regular registers (i.e. non-memory). After reading Steve's
message, I tried a small test case with two-dimensional arrays and my
synthesis tools worked just fine. In other words, you can try define

reg [OUT_WIDTH-1:0] out[PIPELINE_STAGES-1:0];

which is much cleaner.

This assumes (as you have pointed out) that there is a minimum pipeline
delay of 1 but I wonder if it could be arranged so a minimum pipeline
delay
of 0 could be defined. I will have to think about this. Thanks for you
reply.

A conditional generate statement would probably work.

HTH,
Jim
jimwu88NOOOSPAM@yahoo.com (remove capital letters)
http://www.geocities.com/jimwu88/chips

Many thanks.