"alias" problem with `define in sequence detector

[Mahurshi Akilla]

i'm trying to write a detector that would set "Flag" to 1 if a certain
sequence (in this case, 100) is detected.

the code works fine. however, after i introduced the following:
`define MESSAGE 3'b100
and changed my comparision line to:
if (message == MESSAGE)
it complains that "MESSAGE" is undefined.

i thought i could "alias" 3'b100 to MESSAGE so i could change the
detection sequence by only changing the alias and not touching the meat
of the code.

could someone tell me what's wrong here? i am pasting my code below:

`timescale 1ns / 1ps
`define MESSAGE 3'b100
module detector(Din, Reset, clk, Flag);
input Din;
input Reset;
input clk;
output Flag;

reg [2:0] message;
reg Flag;

always @ (posedge clk or posedge Reset)
begin

if (Reset == 1'b1)
begin
message <= 3'b000;
Flag <= 0;
end
else
begin
message <= message << 1;
message[0] <= Din;

if (message == MESSAGE)
begin
Flag <= 1;
end
else
begin
Flag <= 0;
end
end
$display("reset = %d, din = %d, message = %b, flag = %d", Reset, Din,
message, Flag);

end

endmodule

Mahurshi Akilla

 

[Chris Briggs]

That's a simple one. In Verilog, when you refer to a macro created with
`define, you need to reference it with a backtick. I.e., `MESSAGE.

Just to be clear:
`define MESSAGE 3'b100
if (message == `MESSAGE)

-cb

 

[stathis gotsis]

"Mahurshi Akilla" <mahurshi@gmail.com> wrote in message
news:1143477953.053658.123670@e56g2000cwe.googlegroups.com...

i'm trying to write a detector that would set "Flag" to 1 if a certain
sequence (in this case, 100) is detected.

the code works fine. however, after i introduced the following:
`define MESSAGE 3'b100
and changed my comparision line to:
if (message == MESSAGE)
it complains that "MESSAGE" is undefined.

Try comparing to `MESSAGE.

 

[Jason Rosinski]

Mahurshi Akilla wrote:

`define MESSAGE 3'b100
and changed my comparision line to:
if (message == MESSAGE)
it complains that "MESSAGE" is undefined.

Others have already pointed out that you need to use a backtick... But from a stylistic view I'd
point out that you can improve the clarity of the code if you don't rely on case sensitivity in
naming things. I haven't heard of people running into compiler problems while relying on it, but I
think people try to stay away from it. I also find that it helps for certain editing functions to
keep the naming structured.

Something like

`define MSG_TYPE1 3'b100
`define MSG_TYPE2 3'b101
....(etc.)

if (message == `MSG_TYPE1) begin
....whatever
end

 

[Mahurshi Akilla]

stathis gotsis wrote:

"Mahurshi Akilla" <mahurshi@gmail.com> wrote in message
news:1143477953.053658.123670@e56g2000cwe.googlegroups.com...
i'm trying to write a detector that would set "Flag" to 1 if a certain
sequence (in this case, 100) is detected.

the code works fine. however, after i introduced the following:
`define MESSAGE 3'b100
and changed my comparision line to:
if (message == MESSAGE)
it complains that "MESSAGE" is undefined.

Try comparing to `MESSAGE.

Ahh... that fixed the problem. thanks folks.

Mahurshi Akilla

 

[ngsayjoe@gmail.com]

You need `MESSAGE

Joe,
LogicSim - Your Personal Verilog Simulator
http://www.logicsim.com

Mahurshi Akilla wrote:

stathis gotsis wrote:
"Mahurshi Akilla" <mahurshi@gmail.com> wrote in message
news:1143477953.053658.123670@e56g2000cwe.googlegroups.com...
i'm trying to write a detector that would set "Flag" to 1 if a certain
sequence (in this case, 100) is detected.

the code works fine. however, after i introduced the following:
`define MESSAGE 3'b100
and changed my comparision line to:
if (message == MESSAGE)
it complains that "MESSAGE" is undefined.

Try comparing to `MESSAGE.

Ahh... that fixed the problem. thanks folks.

Mahurshi Akilla