Dec 10, 2007 #1 Guest Is anyone using Aldec Riviera-PRO 2007.10 and/or Active_HDL 7.2? If so, do you have any comments or SystemVerilog and/or Verilog examples?
Is anyone using Aldec Riviera-PRO 2007.10 and/or Active_HDL 7.2? If so, do you have any comments or SystemVerilog and/or Verilog examples?
