X
Xilinx User
Guest
I've looked through Aldec's online documentation, but I still can't figure
out the major differences between Active-HDL and Riviera? Also, how much do
they cost (for a Verilog/Systemverilog license)?
out the major differences between Active-HDL and Riviera? Also, how much do
they cost (for a Verilog/Systemverilog license)?