T
Travis Ayres
Guest
I'm getting some errors when I try to compile my design in Aldec's Active-HDL.
# Warning: ELAB1_0026: BITADJ128.bde(BITADJ128.vhd) : (79, 0): There is no default binding for component "buf". (No entity named "buf" was found).
# Warning: ELAB1_0026: BITADJ128.bde(BITADJ128.vhd) : (157, 0): There is no default binding for component "INV". (No entity named "INV" was found).
# Warning: ELAB1_0026: BITADJ128.bde(BITADJ128.vhd) : (277, 0): There is no default binding for component "GND". (No entity named "GND" was found).
I have added these items to the library multiple times, and in different ways, but it still gets hosed up. I'm wondering if anyone else has had a similar issue? I inherited a large design I'm converting from EDIF to VHDL and switching from Virtex-4 to Virtex-5, and there seems to be a symbol resolution problem.
Thanks all!
# Warning: ELAB1_0026: BITADJ128.bde(BITADJ128.vhd) : (79, 0): There is no default binding for component "buf". (No entity named "buf" was found).
# Warning: ELAB1_0026: BITADJ128.bde(BITADJ128.vhd) : (157, 0): There is no default binding for component "INV". (No entity named "INV" was found).
# Warning: ELAB1_0026: BITADJ128.bde(BITADJ128.vhd) : (277, 0): There is no default binding for component "GND". (No entity named "GND" was found).
I have added these items to the library multiple times, and in different ways, but it still gets hosed up. I'm wondering if anyone else has had a similar issue? I inherited a large design I'm converting from EDIF to VHDL and switching from Virtex-4 to Virtex-5, and there seems to be a symbol resolution problem.
Thanks all!