Aggregate for SLV

[xipn]

Hi all,
Is it any tricky way how to extend std_logic_vector by means of aggregate?

Example:
A : STD_LOGIC_VECTOR(3 DOWNTO 0);
B : STD_LOGIC_VECTOR(6 DOWNTO 0);

Something like (see code below)
B <= (5 downto 2 => A, others => '0');

Of course there are a lot of ways how to code it (consequent
assignments, loop,... ) but aggregate would be nice.
Thanks for comments.

-------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY test IS

END ENTITY test;

ARCHITECTURE tb OF test IS

BEGIN -- ARCHITECTURE tb

PROCESS IS

VARIABLE v_x : STD_LOGIC_VECTOR(3 DOWNTO 0) := "1100";
VARIABLE v_y : STD_LOGIC_VECTOR(6 DOWNTO 0);

FUNCTION vec2str(vec : STD_LOGIC_VECTOR) RETURN STRING IS
VARIABLE result : STRING(vec'LEFT + 1 DOWNTO 1);
BEGIN

FOR i IN vec'reverse_range LOOP
IF (vec(i) = '1') THEN
result(i + 1) := '1';
ELSIF (vec(i) = '0') THEN
result(i + 1) := '0';
ELSE
result(i + 1) := 'X';
END IF;
END LOOP;
RETURN result;
END;

BEGIN -- PROCESS

v_y := (5 DOWNTO 2 => '1',OTHERS => '0');
-- v_y := (5 DOWNTO 2 => v_x ,OTHERS => '0');

REPORT "Y = " & vec2str(v_y) & " X = " & vec2str(v_x);
WAIT;

END PROCESS;


END ARCHITECTURE tb;
-------------------------------------------------------------------------------
-- vsim -c test
-- run 1

 

[Paul Uiterlinden]

xipn wrote:

Hi all,
Is it any tricky way how to extend std_logic_vector by means of
aggregate?

Example:
A : STD_LOGIC_VECTOR(3 DOWNTO 0);
B : STD_LOGIC_VECTOR(6 DOWNTO 0);

Something like (see code below)
B <= (5 downto 2 => A, others => '0');

Of course there are a lot of ways how to code it (consequent
assignments, loop,... ) but aggregate would be nice.

With one assignment, using concatenation:
B <= '0' & A & "00";

With two assignments:
B <= (others => '0');
B(5 downto 2) <= A;

--
Paul.
www.aimcom.nl
email address: switch x and s

 

[KJ]

"Paul Uiterlinden" <paulu@sx4all.nl> wrote in message
news:454529c7$0$12516$847b8a10@dreader23...

xipn wrote:

Hi all,
Is it any tricky way how to extend std_logic_vector by means of
aggregate?

Example:
A : STD_LOGIC_VECTOR(3 DOWNTO 0);
B : STD_LOGIC_VECTOR(6 DOWNTO 0);

Something like (see code below)
B <= (5 downto 2 => A, others => '0');

With one assignment, using concatenation:
B <= '0' & A & "00";

With two assignments:
B <= (others => '0');
B(5 downto 2) <= A;

The 'With two assignments' approach will only work when within a process

process(A)
begin
B <= (others => '0');
B(5 downto 2) <= A;
end process;

If used as concurrent statements, then both lines will be driving all 7 bits
of signal 'B'.

KJ

 

[KJ]

If used as concurrent statements, then both lines will be driving all 7
bits of signal 'B'.

Oops, meant to say only bits 5 downto 2 of signal B will have multiple
drivers not all 7

KJ

 

[Paul Uiterlinden]

KJ wrote:

With two assignments:
B <= (others => '0');
B(5 downto 2) <= A;

The 'With two assignments' approach will only work when within a
process

process(A)
begin
B <= (others => '0');
B(5 downto 2) <= A;
end process;

You're right, I forgot to mention that. Thanks for the addition.

--
Paul.
www.aimcom.nl
email address: switch x and s