aggregate assignments

we can do stuff like this:

signal some_signal : std_logic_vector(15 downto 0);

some_signal <= (15 downto 12 => '1', others => '0');

BUT.... is there someway we can do something like this:

some_signal <= (15 downto 12 => "1010", others => '0');

Thanks in advance

 

[Dave]

On Jan 9, 6:57 pm, ed.agu...@gmail.com wrote:

we can do stuff like this:

    signal some_signal : std_logic_vector(15 downto 0);

    some_signal <= (15 downto 12 => '1', others => '0');

BUT.... is there someway we can do something like this:

    some_signal <= (15 downto 12 => "1010", others => '0');

Thanks in advance

How about:

some_signal <= (others => '0');
some_signal(15 downto 12) <= "1010";

Dave

 

[Jonathan Bromley]

On Fri, 9 Jan 2009 17:55:31 -0800 (PST), Dave wrote:

On Jan 9, 6:57 pm, ed.agu...@gmail.com wrote:
is there someway we can do something like this:

    some_signal <= (15 downto 12 => "1010", others => '0');

How about:

some_signal <= (others => '0');
some_signal(15 downto 12) <= "1010";

Yes, that's good, although of course it works only
in procedural code; if it were outside a process,
as concurrent assignments, then you would have
two drivers on (15 downto 12).

Alternatively you could use concatenation:

some_signal <= "1010" & (11 downto 0 => '0');

but that means you lose the explicit subscript
numbers on the top four bits.

Named subscript ranges can sometimes be useful in
this context too:

subtype UPPER_4 is natural range 15 downto 12;
subtype LOWER_12 is natural range 11 downto 0;
...
some_signal(LOWER_12) <= (others => '0');
some_signal(UPPER_4) <= "1010";

And aliases, but that is harder work if you
have lots of signals that you want to work with.
--
Jonathan Bromley, Consultant

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