after the synthesis total logic elements are equal zero

[Andre]

Hi!
I'm trying to synthecize a pic VHDL core on Altera Quartus II web
edition, but when I make changes on the ROM.vhdl(It's using Case-When
clauses), the compiler reports:
; Total logic elements ; 0 ;
; Total pins ; 20 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0

if I don't change the rom program, it reports:
; Total logic elements ; 2,137 ;
; Total pins ; 20 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
..


Someone can tell me why this it happen?

Thank you,
Andre,
Student of science computer - Brazil

 

[Pratip Mukherjee]

andrebt@uai.com.br (Andre) wrote in
news:4bfc232.0401151221.48b9724b@posting.google.com:

Hi!
I'm trying to synthecize a pic VHDL core on Altera Quartus II web
edition, but when I make changes on the ROM.vhdl(It's using Case-When
clauses), the compiler reports:
; Total logic elements ; 0 ;
; Total pins ; 20 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0

if I don't change the rom program, it reports:
; Total logic elements ; 2,137 ;
; Total pins ; 20 ;
; Total memory bits ; 0 ;
; Total PLLs ; 0 ;
.


Someone can tell me why this it happen?

Thank you,
Andre,
Student of science computer - Brazil

Do you have any output pins defined for your top level?