After Place and Route

[ec]

Hi

What if after Place and Route the timing constarint are lower then needed ,
what should be done ?

Should I generate another netlist , or should I try to change the VHDL code
of the model
and then to generate a new netlist and > new place and route ?

Thanks in advace
EC

 

[Mike Treseler]

ec wrote:

What if after Place and Route the timing constarint are lower then needed ,
what should be done ?

Your choices are
1. Reduce the clock frequency.
2. Pipeline the design.
3. Use a faster device.

-- Mike Treseler