AFTER in functional simulations

Hi,

if I describe a register the following way with a registered portion
and a combinational portion then
I can use the AFTER in the registered portion.
The background: I want to perform a functional simulation and
and be sure that the clock edge does not coincide with
signal changes.

---------------------------------------------------------
P_reg: PROCESS(Rst,Clk)
BEGIN
IF Rst='1' THEN
ls_example <= '0';
ELSIF rising_edge(Clk) THEN
ls_example <= next_ls_example AFTER 100 ps;
END IF;
END PROCESS P_reg;

P_comb: PROCESS(ls_example, cond1, cond2, cond3)
BEGIN
next_ls_example <= ls_example;

IF cond1='1' THEN
next_ls_example <= ...;
ELSIF cond2='1' THEN
next_ls_example <= ...;
ELSIF cond3='1' THEN
next_ls_example <= ...;
END IF;
END PROCESS P_comb;
--------------------------------------------------

But what if I use the following single-process approach.
Where do I place the AFTER now ? I mean the example does not include
many assignments but it could be different of course ...

P: PROCESS(Rst, Clk)
BEGIN
IF Rst='1' THEN
ls_example <= '0';
ELSIF rising_edge(Clk) THEN
IF cond1='1' THEN
ls_example <= ...;
ELSIF cond2='1' THEN
ls_example <= ...;
ELSIF cond3='1' THEN
ls_example <= ...;
END IF;
END IF;

END IF;
END PROCESS;

I am trying to simulate my VHDL design which includes a DDR SDRAM
controller IP core. I assume that there is something going wrong
when obtaining data from a template FIFO to provide
data to the IP core.
Does it make sense at all to use AFTER assignments when
performing a functional simulation and all signals generated are
within the FPGA border that is I do not provide stimuli
to the FPGA which could be problematical concerning the rising edge
of the stimuli clock and the signal changes of the stimuli right at the
edge?

Any suggestions are highly appreciated.

Rgds
André