P
Peter Jacobi
Guest
Dear All!
The Fairchild FET models, e.g. for BSS84, BS138 or
Vishay/Siliconix Si4532ADY use subcircuits instead of
a single MOSFET model.
In LTSpice the 2N7002 works the same, nevertheless I
wasn't able to put the other models to work in LTSpice.
I don't think the problem is with the subcircuit, but
that LTSpice uses older MOSFET models, not Level 3?
But perhaps I goofed when moving the files.
Has anybody insights to offer?
Snippet from the Si4532ADY model:
**************************************************************************
..MODEL NMOS NMOS (LEVEL = 3 TOX = 5E-8
+ RS = 11.5E-3 RD = 0 NSUB = 1.6E17
+ kp = 2.6E-5 UO = 650
+ VMAX = 0 XJ = 5E-7 KAPPA = 12E-2
+ ETA = 1E-4 TPG = 1
+ IS = 0 LD = 0
+ CGSO = 0 CGDO = 0 CGBO = 0
+ NFS = 0.8E12 DELTA = 0.1)
***********************************************************************
Are all these parameters supported by LTSpice?
Regards,
Peter Jacobi
The Fairchild FET models, e.g. for BSS84, BS138 or
Vishay/Siliconix Si4532ADY use subcircuits instead of
a single MOSFET model.
In LTSpice the 2N7002 works the same, nevertheless I
wasn't able to put the other models to work in LTSpice.
I don't think the problem is with the subcircuit, but
that LTSpice uses older MOSFET models, not Level 3?
But perhaps I goofed when moving the files.
Has anybody insights to offer?
Snippet from the Si4532ADY model:
**************************************************************************
..MODEL NMOS NMOS (LEVEL = 3 TOX = 5E-8
+ RS = 11.5E-3 RD = 0 NSUB = 1.6E17
+ kp = 2.6E-5 UO = 650
+ VMAX = 0 XJ = 5E-7 KAPPA = 12E-2
+ ETA = 1E-4 TPG = 1
+ IS = 0 LD = 0
+ CGSO = 0 CGDO = 0 CGBO = 0
+ NFS = 0.8E12 DELTA = 0.1)
***********************************************************************
Are all these parameters supported by LTSpice?
Regards,
Peter Jacobi