adding FPGA grounds...

[server]

One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.



--

John Larkin Highland Technology, Inc

Science teaches us to doubt.

Claude Bernard

 

[Lasse Langwadt Christensen]

mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:

One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

if if unused pins are connected to a plane it might help with cooling

 

[Ed Lee]

On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:

mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.

> if if unused pins are connected to a plane it might help with cooling

Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.

I would just let the compiler decide, unless they explicitly stated otherwise in the spec.

 

[Lasse Langwadt Christensen]

mandag den 12. oktober 2020 kl. 02.14.50 UTC+2 skrev Ed Lee:

On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.

default is pulldown because it safe no matter what it is connected to,
the tools don\'t know what you connect the pins to on the pcb

if if unused pins are connected to a plane it might help with cooling

Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.

thermally disconnected ??

I would just let the compiler decide, unless they explicitly stated otherwise in the spec.

the tools doesn\'t know what the pins are connected to it has to pick something safe

 

[Ed Lee]

On Sunday, October 11, 2020 at 5:20:51 PM UTC-7, lang...@fonz.dk wrote:

mandag den 12. oktober 2020 kl. 02.14.50 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.
default is pulldown because it safe no matter what it is connected to,
the tools don\'t know what you connect the pins to on the pcb

if if unused pins are connected to a plane it might help with cooling

Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.
thermally disconnected ??

If not electrically conductive, it\'s also less thermally conductive.

I would just let the compiler decide, unless they explicitly stated otherwise in the spec.
the tools doesn\'t know what the pins are connected to it has to pick something safe

The drivers are likely deactivated, so it\'s doesn\'t matter where it\'s connected to.

 

[Richard Damon]

On 10/11/20 7:17 PM, jlarkin@highlandsniptechnology.com wrote:

One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

I have seen some manufactures suggest this. I haven\'t measured it, but I
would guess it could help, at least as long as the FPGA doesn\'t every
try to drive the output high for a moment.

 

[Lasse Langwadt Christensen]

mandag den 12. oktober 2020 kl. 02.27.18 UTC+2 skrev Ed Lee:

On Sunday, October 11, 2020 at 5:20:51 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 02.14.50 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.
default is pulldown because it safe no matter what it is connected to,
the tools don\'t know what you connect the pins to on the pcb

if if unused pins are connected to a plane it might help with cooling

Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.
thermally disconnected ??

If not electrically conductive, it\'s also less thermally conductive.

the thermal resistance of a mosfet depends on whether it on or off??

I would just let the compiler decide, unless they explicitly stated otherwise in the spec.
the tools doesn\'t know what the pins are connected to it has to pick something safe

The drivers are likely deactivated, so it\'s doesn\'t matter where it\'s connected to.

yes, when they are not activated it doesn\'t matter so the tools have to keep them deactivated, it cannot assume unused pins are connected to ground and turn them on as extra grounds even if it would be an advantage

 

[Ed Lee]

On Sunday, October 11, 2020 at 5:46:42 PM UTC-7, lang...@fonz.dk wrote:

mandag den 12. oktober 2020 kl. 02.27.18 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 5:20:51 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 02.14.50 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.
default is pulldown because it safe no matter what it is connected to,
the tools don\'t know what you connect the pins to on the pcb

if if unused pins are connected to a plane it might help with cooling

Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.
thermally disconnected ??

If not electrically conductive, it\'s also less thermally conductive.
the thermal resistance of a mosfet depends on whether it on or off??

If the cell is activated, it creates heat by itself. I don\'t think it will conduct much heat from another cell, and that it will reduce much net heat. So, turning on a cell just for cooling doesn\'t make much sense.

For noise considerations, perhaps.

 

[Lasse Langwadt Christensen]

mandag den 12. oktober 2020 kl. 02.55.59 UTC+2 skrev Ed Lee:

On Sunday, October 11, 2020 at 5:46:42 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 02.27.18 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 5:20:51 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 02.14.50 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.
default is pulldown because it safe no matter what it is connected to,
the tools don\'t know what you connect the pins to on the pcb

if if unused pins are connected to a plane it might help with cooling

Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.
thermally disconnected ??

If not electrically conductive, it\'s also less thermally conductive.
the thermal resistance of a mosfet depends on whether it on or off??

If the cell is activated, it creates heat by itself. I don\'t think it will conduct much heat from another cell, and that it will reduce much net heat. So, turning on a cell just for cooling doesn\'t make much sense.

For noise considerations, perhaps.

turning on the output doesn\'t matter but soldering the pin to a ground plane might

 

[server]

On Sun, 11 Oct 2020 17:46:33 -0700 (PDT), Lasse Langwadt Christensen
<langwadt@fonz.dk> wrote:

mandag den 12. oktober 2020 kl. 02.27.18 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 5:20:51 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 02.14.50 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.
default is pulldown because it safe no matter what it is connected to,
the tools don\'t know what you connect the pins to on the pcb

if if unused pins are connected to a plane it might help with cooling

Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.
thermally disconnected ??

If not electrically conductive, it\'s also less thermally conductive.

the thermal resistance of a mosfet depends on whether it on or off??

I\'m sure it does, at some parts per million or billion. That would
make a good grad thesis. Charge mobility and such.

I would just let the compiler decide, unless they explicitly stated otherwise in the spec.
the tools doesn\'t know what the pins are connected to it has to pick something safe

The drivers are likely deactivated, so it\'s doesn\'t matter where it\'s connected to.

yes, when they are not activated it doesn\'t matter so the tools have to keep them deactivated, it cannot assume unused pins are connected to ground and turn them on as extra grounds even if it would be an advantage

We can surely force a bunch of pins to be hard low.

Sometimes, not in this case, a compiler will optimize out stuff that
we want. One trick is to have an input pin influence a lot of logic. I
can hardwire that pin high or low, but the compiler doesn\'t know that
so it can\'t optimize my stuff away.

I bet you could build a state machine that winds to making a hard \"1\"
to accomplish the same thing, but is complex enough that the compiler
doesn\'t realize it.




--

John Larkin Highland Technology, Inc

Science teaches us to doubt.

Claude Bernard

 

[Ed Lee]

On Sunday, October 11, 2020 at 8:51:56 PM UTC-7, jla...@highlandsniptechnology.com wrote:

On Sun, 11 Oct 2020 17:46:33 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

mandag den 12. oktober 2020 kl. 02.27.18 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 5:20:51 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 02.14.50 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.
default is pulldown because it safe no matter what it is connected to,
the tools don\'t know what you connect the pins to on the pcb

if if unused pins are connected to a plane it might help with cooling

Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.
thermally disconnected ??

If not electrically conductive, it\'s also less thermally conductive.

the thermal resistance of a mosfet depends on whether it on or off??
I\'m sure it does, at some parts per million or billion. That would
make a good grad thesis. Charge mobility and such.


I would just let the compiler decide, unless they explicitly stated otherwise in the spec.
the tools doesn\'t know what the pins are connected to it has to pick something safe

The drivers are likely deactivated, so it\'s doesn\'t matter where it\'s connected to.

yes, when they are not activated it doesn\'t matter so the tools have to keep them deactivated, it cannot assume unused pins are connected to ground and turn them on as extra grounds even if it would be an advantage



We can surely force a bunch of pins to be hard low.

Sometimes, not in this case, a compiler will optimize out stuff that
we want. One trick is to have an input pin influence a lot of logic. I
can hardwire that pin high or low, but the compiler doesn\'t know that
so it can\'t optimize my stuff away.

I bet you could build a state machine that winds to making a hard \"1\"
to accomplish the same thing, but is complex enough that the compiler
doesn\'t realize it.

I was just questioning the effectiveness of using additional cells for cooling. Especially with output buffer cells, heat transfer to pin/pad is much higher than to any other cells. With smaller geometry, interconnections are getting smaller, but the buffer cells need to be relatively bigger to maintain the current capacity. If anything, you can try to space out cells as much as possible, but i doubt you can do any better than the compiler.

 

[Ricketty C]

On Sunday, October 11, 2020 at 8:14:50 PM UTC-4, Ed Lee wrote:

On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.

Can the compiler connect a pin to the power plane with a via??? I thought the board designer had to do that?

if if unused pins are connected to a plane it might help with cooling

Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.

What does that have to do with cooling??? The pins are only connected to the substrate which is not hard coupled thermally to the IC itself (it is just FR4 or something similar). So there won\'t be much thermal connection. On a flip chip this is entirely a different matter.


> I would just let the compiler decide, unless they explicitly stated otherwise in the spec.

Decide what??? The compiler will configure the I/O pins as you tell it to in your HDL, nothing more, nothing less.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

 

[Ed Lee]

On Sunday, October 11, 2020 at 9:46:59 PM UTC-7, Ricketty C wrote:

On Sunday, October 11, 2020 at 8:14:50 PM UTC-4, Ed Lee wrote:
On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.
Can the compiler connect a pin to the power plane with a via??? I thought the board designer had to do that?
if if unused pins are connected to a plane it might help with cooling


Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.
What does that have to do with cooling???

Nothing. Cell to cell thermal transfer is not that important.

> The pins are only connected to the substrate which is not hard coupled thermally to the IC itself (it is just FR4 or something similar). So there won\'t be much thermal connection.

There are gold wires connecting the cells to pin/pad for electricity and thus heat.

On a flip chip this is entirely a different matter.

I would just let the compiler decide, unless they explicitly stated otherwise in the spec.
Decide what??? The compiler will configure the I/O pins as you tell it to in your HDL, nothing more, nothing less.

Decide what\'s the best configuration when you don\'t tell it to use the pins/pads.

 

[Ricketty C]

On Sunday, October 11, 2020 at 11:51:56 PM UTC-4, jla...@highlandsniptechnology.com wrote:

On Sun, 11 Oct 2020 17:46:33 -0700 (PDT), Lasse Langwadt Christensen
langwadt@fonz.dk> wrote:

mandag den 12. oktober 2020 kl. 02.27.18 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 5:20:51 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 02.14.50 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.
default is pulldown because it safe no matter what it is connected to,
the tools don\'t know what you connect the pins to on the pcb

if if unused pins are connected to a plane it might help with cooling

Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.
thermally disconnected ??

If not electrically conductive, it\'s also less thermally conductive.

the thermal resistance of a mosfet depends on whether it on or off??

I\'m sure it does, at some parts per million or billion. That would
make a good grad thesis. Charge mobility and such.



I would just let the compiler decide, unless they explicitly stated otherwise in the spec.
the tools doesn\'t know what the pins are connected to it has to pick something safe

The drivers are likely deactivated, so it\'s doesn\'t matter where it\'s connected to.

yes, when they are not activated it doesn\'t matter so the tools have to keep them deactivated, it cannot assume unused pins are connected to ground and turn them on as extra grounds even if it would be an advantage




We can surely force a bunch of pins to be hard low.

Sometimes, not in this case, a compiler will optimize out stuff that
we want. One trick is to have an input pin influence a lot of logic. I
can hardwire that pin high or low, but the compiler doesn\'t know that
so it can\'t optimize my stuff away.

I bet you could build a state machine that winds to making a hard \"1\"
to accomplish the same thing, but is complex enough that the compiler
doesn\'t realize it.

The tools do not require there be an input for an output to be driven. If an input does not impact an output the logic it drives may be optimized out and so the input. Or if the logic will only ever drive a single value the logic can be optimized away. But it will never optimize away an output that is driven in the HDL. That output will be driven by a fixed connection.

A <= \'0\';

In VHDL if A is an output from the chip it will be driven to the internal ground level for all time after configuration until the chip is turned off.

Perhaps you are thinking of how software will optimize away code that has no impact on a variable value or something similar.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[Ricketty C]

On Monday, October 12, 2020 at 12:23:56 AM UTC-4, Ed Lee wrote:

On Sunday, October 11, 2020 at 8:51:56 PM UTC-7, jla...@highlandsniptechnology.com wrote:
On Sun, 11 Oct 2020 17:46:33 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

mandag den 12. oktober 2020 kl. 02.27.18 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 5:20:51 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 02.14.50 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.
default is pulldown because it safe no matter what it is connected to,
the tools don\'t know what you connect the pins to on the pcb

if if unused pins are connected to a plane it might help with cooling

Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.
thermally disconnected ??

If not electrically conductive, it\'s also less thermally conductive.

the thermal resistance of a mosfet depends on whether it on or off??
I\'m sure it does, at some parts per million or billion. That would
make a good grad thesis. Charge mobility and such.


I would just let the compiler decide, unless they explicitly stated otherwise in the spec.
the tools doesn\'t know what the pins are connected to it has to pick something safe

The drivers are likely deactivated, so it\'s doesn\'t matter where it\'s connected to.

yes, when they are not activated it doesn\'t matter so the tools have to keep them deactivated, it cannot assume unused pins are connected to ground and turn them on as extra grounds even if it would be an advantage



We can surely force a bunch of pins to be hard low.

Sometimes, not in this case, a compiler will optimize out stuff that
we want. One trick is to have an input pin influence a lot of logic. I
can hardwire that pin high or low, but the compiler doesn\'t know that
so it can\'t optimize my stuff away.

I bet you could build a state machine that winds to making a hard \"1\"
to accomplish the same thing, but is complex enough that the compiler
doesn\'t realize it.

I was just questioning the effectiveness of using additional cells for cooling. Especially with output buffer cells, heat transfer to pin/pad is much higher than to any other cells. With smaller geometry, interconnections are getting smaller, but the buffer cells need to be relatively bigger to maintain the current capacity. If anything, you can try to space out cells as much as possible, but i doubt you can do any better than the compiler.

You are disputing an idea no one has suggested. As Lasse has said, the issue is not about the electrical connection and so not about \"cells\" on the chip. The issue is the thermal connection between the board and the chip through the balls. Provide a hard thermal connection to the power plane to the ball and you will get some additional cooling. Considering that the pad on the board can only be thermally connected to the power plane to a limited extent and the ball on the package only has a limited connection to the chip through the integrated PCB, this will not provide a large measure of thermal relief. How effective this would be could be measured if no specs are provided by the chip company.

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

 

[Ed Lee]

On Sunday, October 11, 2020 at 10:03:19 PM UTC-7, Ricketty C wrote:

On Monday, October 12, 2020 at 12:23:56 AM UTC-4, Ed Lee wrote:
On Sunday, October 11, 2020 at 8:51:56 PM UTC-7, jla...@highlandsniptechnology.com wrote:
On Sun, 11 Oct 2020 17:46:33 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

mandag den 12. oktober 2020 kl. 02.27.18 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 5:20:51 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 02.14.50 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.
default is pulldown because it safe no matter what it is connected to,
the tools don\'t know what you connect the pins to on the pcb

if if unused pins are connected to a plane it might help with cooling

Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.
thermally disconnected ??

If not electrically conductive, it\'s also less thermally conductive.

the thermal resistance of a mosfet depends on whether it on or off??
I\'m sure it does, at some parts per million or billion. That would
make a good grad thesis. Charge mobility and such.


I would just let the compiler decide, unless they explicitly stated otherwise in the spec.
the tools doesn\'t know what the pins are connected to it has to pick something safe

The drivers are likely deactivated, so it\'s doesn\'t matter where it\'s connected to.

yes, when they are not activated it doesn\'t matter so the tools have to keep them deactivated, it cannot assume unused pins are connected to ground and turn them on as extra grounds even if it would be an advantage



We can surely force a bunch of pins to be hard low.

Sometimes, not in this case, a compiler will optimize out stuff that
we want. One trick is to have an input pin influence a lot of logic. I
can hardwire that pin high or low, but the compiler doesn\'t know that
so it can\'t optimize my stuff away.

I bet you could build a state machine that winds to making a hard \"1\"
to accomplish the same thing, but is complex enough that the compiler
doesn\'t realize it.

I was just questioning the effectiveness of using additional cells for cooling. Especially with output buffer cells, heat transfer to pin/pad is much higher than to any other cells. With smaller geometry, interconnections are getting smaller, but the buffer cells need to be relatively bigger to maintain the current capacity. If anything, you can try to space out cells as much as possible, but i doubt you can do any better than the compiler.

You are disputing an idea no one has suggested.

The original suggestion was to compile it low and ground it for cooling, perhaps.

> As Lasse has said, the issue is not about the electrical connection and so not about \"cells\" on the chip. The issue is the thermal connection between the board and the chip through the balls.

So is just adding more solder to the PCB pads, or making bigger pads.

> Provide a hard thermal connection to the power plane to the ball and you will get some additional cooling.

That will only cool the cell you turn on for cooling, not much for other cells.

 

[Ricketty C]

On Monday, October 12, 2020 at 12:54:55 AM UTC-4, Ed Lee wrote:

On Sunday, October 11, 2020 at 9:46:59 PM UTC-7, Ricketty C wrote:
On Sunday, October 11, 2020 at 8:14:50 PM UTC-4, Ed Lee wrote:
On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins..
Can the compiler connect a pin to the power plane with a via??? I thought the board designer had to do that?
if if unused pins are connected to a plane it might help with cooling


Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.
What does that have to do with cooling???

Nothing. Cell to cell thermal transfer is not that important.

Exactly.

The pins are only connected to the substrate which is not hard coupled thermally to the IC itself (it is just FR4 or something similar). So there won\'t be much thermal connection.

There are gold wires connecting the cells to pin/pad for electricity and thus heat.

On a given thickness material, the resistivity gives an ohmic value of resistance per \"square\" meaning a length equal to the width. Equate the round wire to the equivalent square wire and you will get a value of resistance that is not so low for a length equal to the width. Replace thermal units for the electrical units and you will see a total thermal resistance that is pretty high for that very thin wire.

On a flip chip this is entirely a different matter.

I would just let the compiler decide, unless they explicitly stated otherwise in the spec.
Decide what??? The compiler will configure the I/O pins as you tell it to in your HDL, nothing more, nothing less.

Decide what\'s the best configuration when you don\'t tell it to use the pins/pads.

If you don\'t tell it to electrically connect the unneeded pins and it will not connect the unneeded pins.

I\'m sorry, but I have no idea what you think the \"compiler\" is going to do for you??? The tools synthesize what you tell them to synthesize. They don\'t do your thinking for you. Using I/Os to provide electrical grounds is something you must tell the synthesis tool to do.

It is also useful to provide an equal number of power connections through the I/Os since single ended CMOS I/Os use symmetrical voltage levels. The I/Os are just as sensitive to power bounce as they are ground bounce. When outputs pull high, they are drawing current through the power pins and the internal rail and output drives will drop. This will impact the switching threshold as much as ground bounce in CMOS.

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

 

[Ed Lee]

On Sunday, October 11, 2020 at 10:25:20 PM UTC-7, Ricketty C wrote:

On Monday, October 12, 2020 at 12:54:55 AM UTC-4, Ed Lee wrote:
On Sunday, October 11, 2020 at 9:46:59 PM UTC-7, Ricketty C wrote:
On Sunday, October 11, 2020 at 8:14:50 PM UTC-4, Ed Lee wrote:
On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.
Can the compiler connect a pin to the power plane with a via??? I thought the board designer had to do that?
if if unused pins are connected to a plane it might help with cooling


Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.
What does that have to do with cooling???

Nothing. Cell to cell thermal transfer is not that important.
Exactly.
The pins are only connected to the substrate which is not hard coupled thermally to the IC itself (it is just FR4 or something similar). So there won\'t be much thermal connection.

There are gold wires connecting the cells to pin/pad for electricity and thus heat.
On a given thickness material, the resistivity gives an ohmic value of resistance per \"square\" meaning a length equal to the width. Equate the round wire to the equivalent square wire and you will get a value of resistance that is not so low for a length equal to the width. Replace thermal units for the electrical units and you will see a total thermal resistance that is pretty high for that very thin wire.

That thin gold wire is huge compared to the nm interconnecting fabric.

On a flip chip this is entirely a different matter.

I would just let the compiler decide, unless they explicitly stated otherwise in the spec.
Decide what??? The compiler will configure the I/O pins as you tell it to in your HDL, nothing more, nothing less.

Decide what\'s the best configuration when you don\'t tell it to use the pins/pads.
If you don\'t tell it to electrically connect the unneeded pins and it will not connect the unneeded pins.

I\'m sorry, but I have no idea what you think the \"compiler\" is going to do for you??? The tools synthesize what you tell them to synthesize. They don\'t do your thinking for you. Using I/Os to provide electrical grounds is something you must tell the synthesis tool to do.

If you tell the compiler to ground the pin, it will just give you a logical ground. There is no special metal to ground it to the power rail. So, it better to just leave it off and save on power and heat.

 

[Ricketty C]

On Monday, October 12, 2020 at 1:10:01 AM UTC-4, Ed Lee wrote:

On Sunday, October 11, 2020 at 10:03:19 PM UTC-7, Ricketty C wrote:
On Monday, October 12, 2020 at 12:23:56 AM UTC-4, Ed Lee wrote:
On Sunday, October 11, 2020 at 8:51:56 PM UTC-7, jla...@highlandsniptechnology.com wrote:
On Sun, 11 Oct 2020 17:46:33 -0700 (PDT), Lasse Langwadt Christensen
lang...@fonz.dk> wrote:

mandag den 12. oktober 2020 kl. 02.27.18 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 5:20:51 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 02.14.50 UTC+2 skrev Ed Lee:
On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla....@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.
default is pulldown because it safe no matter what it is connected to,
the tools don\'t know what you connect the pins to on the pcb

if if unused pins are connected to a plane it might help with cooling

Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.
thermally disconnected ??

If not electrically conductive, it\'s also less thermally conductive.

the thermal resistance of a mosfet depends on whether it on or off??
I\'m sure it does, at some parts per million or billion. That would
make a good grad thesis. Charge mobility and such.


I would just let the compiler decide, unless they explicitly stated otherwise in the spec.
the tools doesn\'t know what the pins are connected to it has to pick something safe

The drivers are likely deactivated, so it\'s doesn\'t matter where it\'s connected to.

yes, when they are not activated it doesn\'t matter so the tools have to keep them deactivated, it cannot assume unused pins are connected to ground and turn them on as extra grounds even if it would be an advantage



We can surely force a bunch of pins to be hard low.

Sometimes, not in this case, a compiler will optimize out stuff that
we want. One trick is to have an input pin influence a lot of logic.. I
can hardwire that pin high or low, but the compiler doesn\'t know that
so it can\'t optimize my stuff away.

I bet you could build a state machine that winds to making a hard \"1\"
to accomplish the same thing, but is complex enough that the compiler
doesn\'t realize it.

I was just questioning the effectiveness of using additional cells for cooling. Especially with output buffer cells, heat transfer to pin/pad is much higher than to any other cells. With smaller geometry, interconnections are getting smaller, but the buffer cells need to be relatively bigger to maintain the current capacity. If anything, you can try to space out cells as much as possible, but i doubt you can do any better than the compiler.

You are disputing an idea no one has suggested.

The original suggestion was to compile it low and ground it for cooling, perhaps.

I don\'t think anyone said that. The suggestion was simply \"if unused pins are connected to a plane it might help with cooling\"

As Lasse has said, the issue is not about the electrical connection and so not about \"cells\" on the chip. The issue is the thermal connection between the board and the chip through the balls.

So is just adding more solder to the PCB pads, or making bigger pads.

Again, you seem to not understand the nature of the issue. All pads have the same solder balls. The pads on the PCB can be thermally connected to power planes that spread the heat across the board helping to lower the thetaJA. It is hard to make pads any bigger. The issue is providing either a via in pad or a via with a WIDE dog bone (more of a football) to the adjacent via or vias. In fact, if adjacent pins are picked, they can be \"pooled\" and connected to one another (as well as any pins on the same power rail) with all vias in the area connecting the common copper to the same power plane. This would provide the best cooling in aggregate. I guess you could call this a \"wide\" pad.

Provide a hard thermal connection to the power plane to the ball and you will get some additional cooling.

That will only cool the cell you turn on for cooling, not much for other cells.

It has NOTHING to do with \"cells\" or how they are electrically configured. NOTHING The balls are just connections between two PCBs. The chip is connected to one PCB and traces and vias in that PCB connect the chip I/Os to the balls on the other side of that PCB which are then soldered to the PCB you design. No good thermal connection is made over the rather thin traces inside the BGA package. The heat is conducted through the substrate to the balls.

BTW, some BGAs using bond wires and others use a flip chip which solders directly to the internal PCB. Take a look at this page with good illustrations.

https://www.twi-global.com/technical-knowledge/published-papers/a-review-of-ball-grid-arrays-for-electronic-assembly-september-1998?locale=en

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

 

[Ricketty C]

On Monday, October 12, 2020 at 1:36:37 AM UTC-4, Ed Lee wrote:

On Sunday, October 11, 2020 at 10:25:20 PM UTC-7, Ricketty C wrote:
On Monday, October 12, 2020 at 12:54:55 AM UTC-4, Ed Lee wrote:
On Sunday, October 11, 2020 at 9:46:59 PM UTC-7, Ricketty C wrote:
On Sunday, October 11, 2020 at 8:14:50 PM UTC-4, Ed Lee wrote:
On Sunday, October 11, 2020 at 4:31:48 PM UTC-7, lang...@fonz.dk wrote:
mandag den 12. oktober 2020 kl. 01.17.12 UTC+2 skrev jla...@highlandsniptechnology.com:
One of my guys is suggesting that we ground unused balls on an FPGA
and compile them to be low outputs, the idea being to reduce ground
impedance and add some damping.

Has anyone done this? Does it help?

I guess I could have an input that controls the tri-states of all such
pins, and also bring out one logic-low to scope, and turn the grounds
on and off and see if it makes any difference.

It\'s an XC7A15T-1FTG256C with 30 ground pins. We could add at least
another 30 fake grounds.

It was recommended on some older xilinx CPLDs, but I think the general
consensus is that it doesn\'t make much difference on modern BGA FPGAs

The compiler should be smart enough to do what\'s best for unused pins.
Can the compiler connect a pin to the power plane with a via??? I thought the board designer had to do that?
if if unused pins are connected to a plane it might help with cooling


Unused pins are likely disconnected from the rest of the fabric; so, probably not much difference.
What does that have to do with cooling???

Nothing. Cell to cell thermal transfer is not that important.
Exactly.
The pins are only connected to the substrate which is not hard coupled thermally to the IC itself (it is just FR4 or something similar). So there won\'t be much thermal connection.

There are gold wires connecting the cells to pin/pad for electricity and thus heat.
On a given thickness material, the resistivity gives an ohmic value of resistance per \"square\" meaning a length equal to the width. Equate the round wire to the equivalent square wire and you will get a value of resistance that is not so low for a length equal to the width. Replace thermal units for the electrical units and you will see a total thermal resistance that is pretty high for that very thin wire.

That thin gold wire is huge compared to the nm interconnecting fabric.

The size of the transistors and chip features are totally irrelevant.

On a flip chip this is entirely a different matter.

I would just let the compiler decide, unless they explicitly stated otherwise in the spec.
Decide what??? The compiler will configure the I/O pins as you tell it to in your HDL, nothing more, nothing less.

Decide what\'s the best configuration when you don\'t tell it to use the pins/pads.
If you don\'t tell it to electrically connect the unneeded pins and it will not connect the unneeded pins.

I\'m sorry, but I have no idea what you think the \"compiler\" is going to do for you??? The tools synthesize what you tell them to synthesize. They don\'t do your thinking for you. Using I/Os to provide electrical grounds is something you must tell the synthesis tool to do.

If you tell the compiler to ground the pin, it will just give you a logical ground. There is no special metal to ground it to the power rail. So, it better to just leave it off and save on power and heat.

I think you don\'t understand how CMOS devices work. Please do some reading on the structure of a CMOS output. When a MOS transistor is turned on it provides an electrical connection between the drain and source. In this case one is connected to a power rail and the other to an output pin. That\'s a low(ish) impedance connection which is only different from a metal connection in terms of the impedance. But any connection is better than none. The \"logic\" is not at issue in any way.

--

Rick C.

++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209