Adding a NATURAL and a STD_LOGIC_VECTOR

  • Thread starter Sebastien Bourdeauducq
  • Start date
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Sebastien Bourdeauducq

Guest
Hi,

I'd like to compute the arithmetic sum of a NATURAL signal and a
STD_LOGIC_VECTOR signal, and store the value into a NATURAL signal,
ie. a <= b + c, with a NATURAL, b NATURAL and c STD_LOGIC_VECTOR.
How should I do ? Here the compiler complains about not finding a
suitable definition of the + operator. I tried various combinations of
TO_INTEGER(), TO_BIT_VECTOR(), UNSIGNED(), ... but no luck.
The sum works when all operands are NATURAL.

I'm using Quartus II from Altera.

Regards,

Sebastien
 
On Jun 8, 7:31 am, Sebastien Bourdeauducq
<sebastien.bourdeaud...@gmail.com> wrote:
Hi,

I'd like to compute the arithmetic sum of a NATURAL signal and a
STD_LOGIC_VECTOR signal, and store the value into a NATURAL signal,
ie. a <= b + c, with a NATURAL, b NATURAL and c STD_LOGIC_VECTOR.
How should I do ? Here the compiler complains about not finding a
suitable definition of the + operator. I tried various combinations of
TO_INTEGER(), TO_BIT_VECTOR(), UNSIGNED(), ... but no luck.
The sum works when all operands are NATURAL.

I'm using Quartus II from Altera.

Regards,

Sebastien
Click to expand...
use ieee.numeric_std.all;

....

a <= to_integer(b + unsigned(c));

or:

a <= b + to_integer(unsigned(c));


Andy
 
"Sebastien Bourdeauducq" <sebastien.bourdeauducq@gmail.com> wrote in message
news:1181305889.141918.122340@w5g2000hsg.googlegroups.com...
Hi,

I'd like to compute the arithmetic sum of a NATURAL signal and a
STD_LOGIC_VECTOR signal, and store the value into a NATURAL signal,
ie. a <= b + c, with a NATURAL, b NATURAL and c STD_LOGIC_VECTOR.
How should I do ? Here the compiler complains about not finding a
suitable definition of the + operator. I tried various combinations of
TO_INTEGER(), TO_BIT_VECTOR(), UNSIGNED(), ... but no luck.
The sum works when all operands are NATURAL.
Click to expand...
The base VHDL language (through VHDL-2002) does not define arithmetic on
std_logic_vectors. You have to use an external package (or write the
addition operator yourself) to get the desired functionality. Following the
IEEE standard approach, you will need to use package IEEE.numeric_std from
1076.3-1997. If IN1 and OUT1 are std_logic_vectors of the same length, and
IN2 is of type NATURAL, the following assignment works:

out1 <= std_logic_vector( unsigned(in1) + in2 );

This a) converts IN1 from SLV to UNSIGNED, b) performs the addition
creating an UNSIGNED result, and c) converts the result back to SLV.

Some alternative approaches:
Using Synopsys' package IEEE.std_logic_arith: out1 <= unsigned(in1) + in2;
Using Synopsys' package IEEE.std_logic_unsigned: out1 <= in1 + in2;
 
a <= b + to_integer(unsigned(c)); with ieee.numeric_std.all works.
Thanks !
 
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