Add up N signed numbers in parallel.

[goannae]

Hi everyone,



I would like to add up (in parallel) N 2-bit signed numbers (which are
generated from an inner product b/w two vectors). The target FPGA is
vertex-2. I am considering using a 4-2 compressor tree. I am wondering if
this is a right choice. Also, can I generate the circuit with generate and
recursion? I am using modelsim SE 6.1.



Any help would be greatly appreciated.



goanna

 

[John_H]

goannae wrote:

Hi everyone,



I would like to add up (in parallel) N 2-bit signed numbers (which are
generated from an inner product b/w two vectors). The target FPGA is
vertex-2. I am considering using a 4-2 compressor tree. I am wondering if
this is a right choice. Also, can I generate the circuit with generate and
recursion? I am using modelsim SE 6.1.



Any help would be greatly appreciated.



goanna

I'm not sure what you mean by "4-2 compressor tree."

Is your end result from -N to +N, inclusive, or is it the full range of
+N to -2*N, inclusive? The latter case is more straight forward but the
former is interesting.

If your range is +N to -N, you may get better (faster) results by
assembling 3-bit signed values as the lowest stage with a +3 to -3 range
and adding up in a tree from there. If all you're interested in is +1,
0, or -1, I'd think you'd get cleaner results by encoding two bits as
"plus1" and "minus1" where only one or neither of the values is
asserted. You might extend to a first stage with 4-bit signed values
(+7 to -7) with optimized resource usage.

I'd think you could use recursion with generates to handle the middle or
end (no more recursion) cases but good handling of recursion may be up
to the tools. There's been a discussion on recursion by those more
concerned with it on this newsgroup in recent days; I'd suggest reading
through those posts if you haven't already. The thread "Recursive
instantiation: a synthesis no no?" started July 11th 2006.