add-compare-select

[Matthias Alles]

Hi!

I'm trying to implement an add-compare-select (ACS) unit in a Spartan3
but I am not satisfied with the speed. The code looks like this:

....
type sum_array is array(0 to 7) of signed(13 downto 0);
signal state_reg : sum_array;
....

process(clk, rst) is

variable sum1, sum2, sum3, sum4 : sum_array;

begin
if rst = '1' then
....
elsif clk'event and clk = '1' then

...

sum1(0) := state_reg(a1) + gamma(a2);
sum2(0) := state_reg(b1) + gamma(b2);
sum3(0) := state_reg(c1) + gamma(c2);
sum4(0) := state_reg(d1) + gamma(d2);

state_reg(0) <= MIN4(sum1(0), sum2(0), sum3(0), sum4(0));

...
end if; -- rst,clk
end process;

where a1, a2, ..., d2 are some constants. The problem with this code is
that we access the newly calculated state_reg in the very next clock
cycle (the constants can be for instance zero!). Hence pipelining is not
possible. The Minimum search (MIN4) is done by doing 6 subtractions in
parallel to avoid a two stage minimum search tree.
I would like to boost the clock frequency of this architecture. Is there
a way to further improve the description in VHDL? Or is it possible to
do some hand optimisations?

Thanks in advance,
Matthias

 

[Sylvain Munaut]

Matthias Alles wrote:

I'm trying to implement an add-compare-select (ACS) unit in a Spartan3
but I am not satisfied with the speed. The code looks like this:

What's the current speed ?
What would you like to achieve ?

...
type sum_array is array(0 to 7) of signed(13 downto 0);
signal state_reg : sum_array;
...

process(clk, rst) is

variable sum1, sum2, sum3, sum4 : sum_array;

begin
if rst = '1' then
....
elsif clk'event and clk = '1' then

...

sum1(0) := state_reg(a1) + gamma(a2);
sum2(0) := state_reg(b1) + gamma(b2);
sum3(0) := state_reg(c1) + gamma(c2);
sum4(0) := state_reg(d1) + gamma(d2);

state_reg(0) <= MIN4(sum1(0), sum2(0), sum3(0), sum4(0));

...
end if; -- rst,clk
end process;

where a1, a2, ..., d2 are some constants. The problem with this code is
that we access the newly calculated state_reg in the very next clock
cycle (the constants can be for instance zero!). Hence pipelining is not
possible. The Minimum search (MIN4) is done by doing 6 subtractions in
parallel to avoid a two stage minimum search tree.
I would like to boost the clock frequency of this architecture. Is there
a way to further improve the description in VHDL? Or is it possible to
do some hand optimisations?

Are the gamma constants ?

The only thing I see from a quick look is that you could "post-pone" part of
the minimum mux.

For now, you have a MUX4 between the 4 sums. You could just assign
state_reg_a to min2(sum1,sum2) and state_reg_b to min2(sum3,sum4). Then
register the output of your other comparaison (to know whick of _a or _b is the
good one), then do the mux the cycle after. And that mux can fit within the same
LUT as the one that does the addition.

I have no idea if it will be really that much faster (or faster at all) because
all you gain is a F5 mux and that gain could be couteracted by other factors ...


You can also take a faster speedgrade


Sylvain

 

sir i need vhdl code for viterbi decoder please snd me the code sir

 

[Andy Bartlett]

<fabtn2012@gmail.com> wrote in message
news:0f2a1599-33da-4185-84ca-fca384618c30@googlegroups.com...

sir i need vhdl code for viterbi decoder please snd me the code sir

Sure no problem. Please make check out for Ł2350 + Vat.

 

[Tim Wescott]

On Sun, 24 Feb 2013 16:24:28 +0000, Andy Bartlett wrote:

fabtn2012@gmail.com> wrote in message
news:0f2a1599-33da-4185-84ca-fca384618c30@googlegroups.com...
sir i need vhdl code for viterbi decoder please snd me the code sir

Sure no problem. Please make check out for ÂŁ2350 + Vat.

One does wonder just what people think is on the other end of the
conversation in a newsgroup.

Like Andy, I'm not going to work for free, but I'll happily help you out
if you contact me off-group, with money in hand.

--
My liberal friends think I'm a conservative kook.
My conservative friends think I'm a liberal kook.
Why am I not happy that they have found common ground?

Tim Wescott, Communications, Control, Circuits & Software
http://www.wescottdesign.com

 

[glen herrmannsfeldt]

Tim Wescott <tim@seemywebsite.com> wrote:

On Sun, 24 Feb 2013 16:24:28 +0000, Andy Bartlett wrote:

fabtn2012@gmail.com> wrote in message
news:0f2a1599-33da-4185-84ca-fca384618c30@googlegroups.com...
sir i need vhdl code for viterbi decoder please snd me the code sir

Sure no problem. Please make check out for Ł2350 + Vat.

One does wonder just what people think is on the other end of the
conversation in a newsgroup.

Like Andy, I'm not going to work for free, but I'll happily help you out
if you contact me off-group, with money in hand.

It is certainly possible that one exists in, for example, opencores.

In that case, if one did reply, it would usually be with the link to
the site and not the actual code.

Anyone remember the movie "Back to the Future" when the main character
goes to a lunch counter and orders a "Pepsi Free" (which didn't yet
exist)?

-- glen

 

[Tim Wescott]

On Mon, 25 Feb 2013 19:24:41 +0000, glen herrmannsfeldt wrote:

Tim Wescott <tim@seemywebsite.com> wrote:
On Sun, 24 Feb 2013 16:24:28 +0000, Andy Bartlett wrote:

fabtn2012@gmail.com> wrote in message
news:0f2a1599-33da-4185-84ca-fca384618c30@googlegroups.com...
sir i need vhdl code for viterbi decoder please snd me the code sir

Sure no problem. Please make check out for ÂŁ2350 + Vat.

One does wonder just what people think is on the other end of the
conversation in a newsgroup.

Like Andy, I'm not going to work for free, but I'll happily help you
out if you contact me off-group, with money in hand.

It is certainly possible that one exists in, for example, opencores.

In that case, if one did reply, it would usually be with the link to the
site and not the actual code.

I should probably have pointed that out. "I need code, send it to me"
just pushes a button with me, even though I know it's usually some
student, possibly foreign, who is not being rude on purpose.

Sigh. I suppose I could give up being a curmudgeon for Lent, but then
where would I be?

--
Tim Wescott
Control system and signal processing consulting
www.wescottdesign.com