ADCs in FPGAs...

[Rick C]

I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I\'m not completely clear on how to do it.

Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input.. I\'m having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?

Anyone built one of these? Is it practical to expect 12 bits of resolution with a 16 MHz clock rate and 1 kHz sample rate? By 12 bits I mean a solid 12 bits of accuracy... the word width can be wider if that helps any.

--

Rick C.

- Get 1,000 miles of free Supercharging
- Tesla referral code - https://ts.la/richard11209

 

[David Brown]

On 31/08/2020 02:57, Rick C wrote:

I have looked at ADCs in FPGAs but never built one. Obviously sigma
delta is a good way to go as it can be done all digitally, or almost
so. I\'m not completely clear on how to do it.

Lattice has a reference design using an LVDS receiver as a
comparator. They use an RC filter on the output bit as the reference
voltage for the input. I\'m having trouble relating this to the
typical block diagram of the sigma delta converter. Is this circuit
the same thing?

Anyone built one of these? Is it practical to expect 12 bits of
resolution with a 16 MHz clock rate and 1 kHz sample rate? By 12
bits I mean a solid 12 bits of accuracy... the word width can be
wider if that helps any.

I would not be confident at getting 12 bits accuracy inside a fast
digital part - it\'s very difficult to have your supplies and references
stable enough, and to avoid switching noise from the digital parts
interfering with the analogue. A 1 kHz sample rate 14-bit ADC chip with
SPI or I²C shouldn\'t cost much or take much space.

 

[Michael Kellett]

On 31/08/2020 01:57, Rick C wrote:

I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I\'m not completely clear on how to do it.

Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I\'m having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?

Anyone built one of these? Is it practical to expect 12 bits of resolution with a 16 MHz clock rate and 1 kHz sample rate? By 12 bits I mean a solid 12 bits of accuracy... the word width can be wider if that helps any.

I\'ve never tried - getting a decent ADC into a functioning FPGA seems
like a very difficult task.
Microchip have some nice, cheap, multichannel parts, the MCP3461/2/4
will do you, it has programmable gain, multiplexer, choice of up to 8
channels, 15 ENOB etc.

MK

 

[Rick C]

On Monday, August 31, 2020 at 4:32:56 AM UTC-4, Michael Kellett wrote:

On 31/08/2020 01:57, Rick C wrote:
I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I\'m not completely clear on how to do it.

Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I\'m having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?

Anyone built one of these? Is it practical to expect 12 bits of resolution with a 16 MHz clock rate and 1 kHz sample rate? By 12 bits I mean a solid 12 bits of accuracy... the word width can be wider if that helps any.

I\'ve never tried - getting a decent ADC into a functioning FPGA seems
like a very difficult task.
Microchip have some nice, cheap, multichannel parts, the MCP3461/2/4
will do you, it has programmable gain, multiplexer, choice of up to 8
channels, 15 ENOB etc.

MK

Yes, I looked at that part. It\'s not as available as our target which is 10,000 stocked... yes, that may sound unrealistic, but many devices meet that requirement even if the FPGAs typically don\'t. Also it is a bit complicated to use. Configuring it from an FPGA is a bother... configuring it from anything is a bother. lol But it certainly is an option. Very likely I will include both options, internal ADC and external ADC. I\'m not convinced I can\'t get a decent 12 bit ADC using an LVDS I/O. The I/O banks have separate power and ground pins, so that reduces the switching currents. Also, this is a very low power chip. It\'s not your city dimmer Virtex.

The irony is I wanted to go with a Gowin part because of the limited I/O count and lack of LVDS on the iCE40 Ultra parts. Moving the ADC to a dedicated chip frees up enough I/Os the iCE40 Ultra 39 I/O count works. Still need a comparator or two for other functions that could be in the FPGA. I suppose I could justify the Gowin part in the 48QFN which still has LVDS for comparators.

I just got a call from Edge, a Gowin distributor. I guess they take seriously inquiries of qty 10,000.

--

Rick C.

+ Get 1,000 miles of free Supercharging
+ Tesla referral code - https://ts.la/richard11209

 

[server]

mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C:

I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I\'m not completely clear on how to do it.

Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I\'m having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?

I\'d say it is a delta modulator not a delta-sigma modulator

 

[Rick C]

On Monday, August 31, 2020 at 5:43:54 PM UTC-4, lasselangwad...@gmail.com wrote:

mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C:
I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I\'m not completely clear on how to do it.

Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I\'m having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?


I\'d say it is a delta modulator not a delta-sigma modulator

Sorry, I\'m not clear on what distinction you are trying to make. First, what is \"it\"?

--

Rick C.

-- Get 1,000 miles of free Supercharging
-- Tesla referral code - https://ts.la/richard11209

 

[server]

tirsdag den 1. september 2020 kl. 00.29.02 UTC+2 skrev Rick C:

On Monday, August 31, 2020 at 5:43:54 PM UTC-4, lasselangwad...@gmail.com wrote:
mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C:
I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I\'m not completely clear on how to do it.

Lattice has a reference design using an LVDS receiver as a comparator.. They use an RC filter on the output bit as the reference voltage for the input. I\'m having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?


I\'d say it is a delta modulator not a delta-sigma modulator

Sorry, I\'m not clear on what distinction you are trying to make. First, what is \"it\"?

the commonly used \"RC filter on the output bit used as reference voltage\" I\'d call a delta modulator

in a delta-sigma input minus output is integrated and the reference voltage fixed

 

[Rick C]

On Thursday, September 3, 2020 at 7:39:18 PM UTC-4, lasselangwad...@gmail.com wrote:

tirsdag den 1. september 2020 kl. 00.29.02 UTC+2 skrev Rick C:
On Monday, August 31, 2020 at 5:43:54 PM UTC-4, lasselangwad...@gmail.com wrote:
mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C:
I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I\'m not completely clear on how to do it.

Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I\'m having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?


I\'d say it is a delta modulator not a delta-sigma modulator

Sorry, I\'m not clear on what distinction you are trying to make. First, what is \"it\"?


the commonly used \"RC filter on the output bit used as reference voltage\" I\'d call a delta modulator

in a delta-sigma input minus output is integrated and the reference voltage fixed

Ok, I understand what you mean now. That is what I was asking about. Thanks

--

Rick C.

-+ Get 1,000 miles of free Supercharging
-+ Tesla referral code - https://ts.la/richard11209

 

[Rick C]

On Thursday, September 3, 2020 at 7:39:18 PM UTC-4, lasselangwad...@gmail.com wrote:

tirsdag den 1. september 2020 kl. 00.29.02 UTC+2 skrev Rick C:
On Monday, August 31, 2020 at 5:43:54 PM UTC-4, lasselangwad...@gmail.com wrote:
mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C:
I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I\'m not completely clear on how to do it.

Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I\'m having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?


I\'d say it is a delta modulator not a delta-sigma modulator

Sorry, I\'m not clear on what distinction you are trying to make. First, what is \"it\"?


the commonly used \"RC filter on the output bit used as reference voltage\" I\'d call a delta modulator

in a delta-sigma input minus output is integrated and the reference voltage fixed

Here is my thinking. Some people talk about digital noise being the source of noise limitations in this technique. The I/O bank on FPGAs are separate from the rest of the chip and each other. We have plenty of spare I/Os so we can dedicate a bank to ADC use. Then the I/Os for the ADC are not just less noisy, but also it can be provided by it\'s own supply with lower noise and better accuracy... or more like tracking the 5 volt rail that powers the sensors.

I\'ve been mulling the distinction between delta-sigma (or sigma-delta, I can never remember) and the delta modulator. A simple mod to the analog circuit should make it a delta-sigma.

Vref -----------------| Vin-
|
Vin ---RRR---o---o----| Vin+
| | |
R --- |
R --- |
R | |
| V |
| |
+--------| SD out

This should provide the integration and quantization to be sigma-delta, right?

The part I\'m not clear on is turning the bit stream into a number. I believe the Lattice design simply counts the 1\'s on the comparator output. Does that constitute a first order filter?

We can run this input at up to 33 MHz. At that rate we should have plenty of samples to work with. Do you think we could potentially eke out a solid 12 bits of performance with a sample rate of 1 kHz?

I\'ve seen this discussed a lot, but never ran into anyone who has done it. We now have four or five people on the electronic design part and things are moving so fast, I\'m not sure there will be time to give this proper consideration. Even though the motor, mechanicals and other parts are not designed fully yet they want to push on the circuit board.

Someone said they had used an instantiated ADC in the Xilinx tools. Anyone know if that is actually an ADC or if it is an ADC chip interface?

--

Rick C.

+- Get 1,000 miles of free Supercharging
+- Tesla referral code - https://ts.la/richard11209

 

[Stef]

On 2020-10-23 Rick C wrote in comp.arch.fpga:

Someone said they had used an instantiated ADC in the Xilinx tools. Anyone know if that is actually an ADC or if it is an ADC chip interface?

On what Xilinx device? At least the Zynq devices do have actual ADC\'s.

--
Stef (remove caps, dashes and .invalid from e-mail address to reply by mail)

I\'m a fuschia bowling ball somewhere in Brittany

 

[server]

fredag den 23. oktober 2020 kl. 07.10.53 UTC+2 skrev Rick C:

On Thursday, September 3, 2020 at 7:39:18 PM UTC-4, lasselangwad...@gmail..com wrote:
tirsdag den 1. september 2020 kl. 00.29.02 UTC+2 skrev Rick C:
On Monday, August 31, 2020 at 5:43:54 PM UTC-4, lasselangwad...@gmail..com wrote:
mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C:
I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so.. I\'m not completely clear on how to do it.

Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I\'m having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?


I\'d say it is a delta modulator not a delta-sigma modulator

Sorry, I\'m not clear on what distinction you are trying to make. First, what is \"it\"?


the commonly used \"RC filter on the output bit used as reference voltage\" I\'d call a delta modulator

in a delta-sigma input minus output is integrated and the reference voltage fixed

Here is my thinking. Some people talk about digital noise being the source of noise limitations in this technique. The I/O bank on FPGAs are separate from the rest of the chip and each other. We have plenty of spare I/Os so we can dedicate a bank to ADC use. Then the I/Os for the ADC are not just less noisy, but also it can be provided by it\'s own supply with lower noise and better accuracy... or more like tracking the 5 volt rail that powers the sensors.

I\'ve been mulling the distinction between delta-sigma (or sigma-delta, I can never remember) and the delta modulator. A simple mod to the analog circuit should make it a delta-sigma.

Vref -----------------| Vin-
|
Vin ---RRR---o---o----| Vin+
| | |
R --- |
R --- |
R | |
| V |
| |
+--------| SD out

This should provide the integration and quantization to be sigma-delta, right?

yes with the voltage on Vin almost constant it should be an ok approximation,
how well it works in practice I don\'t know

The part I\'m not clear on is turning the bit stream into a number. I believe the Lattice design simply counts the 1\'s on the comparator output. Does that constitute a first order filter?

number of 1\'s ever a period should aka. integrate and dump has a sinc frequency
response

https://en.wikipedia.org/wiki/Sinc_filter#Frequency-domain_sinc

We can run this input at up to 33 MHz. At that rate we should have plenty of samples to work with. Do you think we could potentially eke out a solid 12 bits of performance with a sample rate of 1 kHz?

I don\'t know, I think only of the Xilinx app notes has some examples of performance

I\'ve seen this discussed a lot, but never ran into anyone who has done it.. We now have four or five people on the electronic design part and things are moving so fast, I\'m not sure there will be time to give this proper consideration. Even though the motor, mechanicals and other parts are not designed fully yet they want to push on the circuit board.

Someone said they had used an instantiated ADC in the Xilinx tools. Anyone know if that is actually an ADC or if it is an ADC chip interface?

some Xilinx ICs has buildin ADC, with a as far as I know optimistic 12bit

 

[Rick C]

On Friday, October 23, 2020 at 3:02:53 AM UTC-4, Stef wrote:

On 2020-10-23 Rick C wrote in comp.arch.fpga:

Someone said they had used an instantiated ADC in the Xilinx tools. Anyone know if that is actually an ADC or if it is an ADC chip interface?

On what Xilinx device? At least the Zynq devices do have actual ADC\'s.

Don\'t know yet. I\'m asking questions, but he specifically said instantiated \"IP\" but I suppose that might be the same as \"instantiating\" a clock block with PLL ect.

I\'m essentially interviewing him to work on this open source project and the real issue is how much he knows about delta-sigma converters and how to implement them.

Right now I\'d like to get an idea of whether it would significantly improve accuracy and/or noise to use separate comparator and driver for the analog interface. The sensors are powered from 5 volts and so produce a 5 volt analog output. The separate drivers and comparators could be powered from the same supply, separate from any other supply on the board for noise isolation. Also, as the sensor outputs are proportional to the power rail voltage, this will make all measurements ratiometric eliminating the need to correct for the power voltages. Otherwise we need to provide the I/O bank 3.3 volts that is a ratioed to the 5 volt rail. I guess no big deal. The point is it\'s not that much more to use separate comparators and drivers and may get us noise and accuracy advantages.

Sorry if this sounds irrelevant. I often uses newsgroup posts to solidify my thinking. In this case we have tons of I/Os available, so I think I\'m going to use both approaches and dedicate a bank of I/Os to the ADCs.

--

Rick C.

++ Get 1,000 miles of free Supercharging
++ Tesla referral code - https://ts.la/richard11209

 

[Rick C]

On Friday, October 23, 2020 at 1:35:45 PM UTC-4, lasselangwad...@gmail.com wrote:

fredag den 23. oktober 2020 kl. 07.10.53 UTC+2 skrev Rick C:
On Thursday, September 3, 2020 at 7:39:18 PM UTC-4, lasselangwad...@gmail.com wrote:
tirsdag den 1. september 2020 kl. 00.29.02 UTC+2 skrev Rick C:
On Monday, August 31, 2020 at 5:43:54 PM UTC-4, lasselangwad...@gmail.com wrote:
mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C:
I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I\'m not completely clear on how to do it.

Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I\'m having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?


I\'d say it is a delta modulator not a delta-sigma modulator

Sorry, I\'m not clear on what distinction you are trying to make. First, what is \"it\"?


the commonly used \"RC filter on the output bit used as reference voltage\" I\'d call a delta modulator

in a delta-sigma input minus output is integrated and the reference voltage fixed

Here is my thinking. Some people talk about digital noise being the source of noise limitations in this technique. The I/O bank on FPGAs are separate from the rest of the chip and each other. We have plenty of spare I/Os so we can dedicate a bank to ADC use. Then the I/Os for the ADC are not just less noisy, but also it can be provided by it\'s own supply with lower noise and better accuracy... or more like tracking the 5 volt rail that powers the sensors.

I\'ve been mulling the distinction between delta-sigma (or sigma-delta, I can never remember) and the delta modulator. A simple mod to the analog circuit should make it a delta-sigma.

Vref -----------------| Vin-
|
Vin ---RRR---o---o----| Vin+
| | |
R --- |
R --- |
R | |
| V |
| |
+--------| SD out

This should provide the integration and quantization to be sigma-delta, right?

yes with the voltage on Vin almost constant it should be an ok approximation,
how well it works in practice I don\'t know

Not sure what you mean about constant Vin. Vin is the signal being measured. Of course it needs to be band limited, but a main point of delta-sigma is that band is at the Nyquist rate of the input samples, a much wider band than the output band.

I\'m also not sure why you refer to this as an approximation. The resistors are performing the difference of the input and the feedback. The cap is the integrator. I suppose it\'s not a perfect integrator. Is it essentially equivalent to the other input circuit with the signal input as Vref and an RC from the feedback output to the differential input? Our decimation factor will be on the order of 32kibi.

One difference is the original circuit will run the inputs over a common mode range of 0 to Vcc. The above circuit will keep the inputs near Vref.

The part I\'m not clear on is turning the bit stream into a number. I believe the Lattice design simply counts the 1\'s on the comparator output. Does that constitute a first order filter?

number of 1\'s ever a period should aka. integrate and dump has a sinc frequency
response

https://en.wikipedia.org/wiki/Sinc_filter#Frequency-domain_sinc

Yeah, I know that. I just haven\'t done it before myself, so I\'m unsure of what works well and what doesn\'t.

We can run this input at up to 33 MHz. At that rate we should have plenty of samples to work with. Do you think we could potentially eke out a solid 12 bits of performance with a sample rate of 1 kHz?


I don\'t know, I think only of the Xilinx app notes has some examples of performance


I\'ve seen this discussed a lot, but never ran into anyone who has done it. We now have four or five people on the electronic design part and things are moving so fast, I\'m not sure there will be time to give this proper consideration. Even though the motor, mechanicals and other parts are not designed fully yet they want to push on the circuit board.

Someone said they had used an instantiated ADC in the Xilinx tools. Anyone know if that is actually an ADC or if it is an ADC chip interface?


some Xilinx ICs has buildin ADC, with a as far as I know optimistic 12bit

Not using Xilinx for many reasons, but the big one is cost. Xilinx is great if you are designing dense FPGAs, but not so good if you are using an FPGA like one of the small ARM devices. Gowin has good packages and lots of differential I/Os and great pricing. Lattice has some good packages, but seem to have dropped the ball on the I/Os, very limited differential options in the good packages. I wouldn\'t be using Gowin otherwise.

--

Rick C.

--- Get 1,000 miles of free Supercharging
--- Tesla referral code - https://ts.la/richard11209

 

[server]

fredag den 23. oktober 2020 kl. 20.28.58 UTC+2 skrev Rick C:

On Friday, October 23, 2020 at 1:35:45 PM UTC-4, lasselangwad...@gmail.com wrote:
fredag den 23. oktober 2020 kl. 07.10.53 UTC+2 skrev Rick C:
On Thursday, September 3, 2020 at 7:39:18 PM UTC-4, lasselangwad...@gmail.com wrote:
tirsdag den 1. september 2020 kl. 00.29.02 UTC+2 skrev Rick C:
On Monday, August 31, 2020 at 5:43:54 PM UTC-4, lasselangwad...@gmail.com wrote:
mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C:
I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I\'m not completely clear on how to do it.

Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I\'m having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?


I\'d say it is a delta modulator not a delta-sigma modulator

Sorry, I\'m not clear on what distinction you are trying to make. First, what is \"it\"?


the commonly used \"RC filter on the output bit used as reference voltage\" I\'d call a delta modulator

in a delta-sigma input minus output is integrated and the reference voltage fixed

Here is my thinking. Some people talk about digital noise being the source of noise limitations in this technique. The I/O bank on FPGAs are separate from the rest of the chip and each other. We have plenty of spare I/Os so we can dedicate a bank to ADC use. Then the I/Os for the ADC are not just less noisy, but also it can be provided by it\'s own supply with lower noise and better accuracy... or more like tracking the 5 volt rail that powers the sensors.

I\'ve been mulling the distinction between delta-sigma (or sigma-delta, I can never remember) and the delta modulator. A simple mod to the analog circuit should make it a delta-sigma.

Vref -----------------| Vin-
|
Vin ---RRR---o---o----| Vin+
| | |
R --- |
R --- |
R | |
| V |
| |
+--------| SD out

This should provide the integration and quantization to be sigma-delta, right?

yes with the voltage on Vin almost constant it should be an ok approximation,
how well it works in practice I don\'t know

Not sure what you mean about constant Vin. Vin is the signal being measured.

I meant Vin+ the comparator input

Of course it needs to be band limited, but a main point of delta-sigma is that band is at the Nyquist rate of the input samples, a much wider band than the output band.

I\'m also not sure why you refer to this as an approximation. The resistors are performing the difference of the input and the feedback. The cap is the integrator. I suppose it\'s not a perfect integrator. Is it essentially equivalent to the other input circuit with the signal input as Vref and an RC from the feedback output to the differential input? Our decimation factor will be on the order of 32kibi.

an ideal integrator would charge the cap with a current proportional to the Vin
for that to happen Vin+ would need to be constant, it isn\'t quite

 

[server]

fredag den 23. oktober 2020 kl. 20.07.58 UTC+2 skrev Rick C:

On Friday, October 23, 2020 at 3:02:53 AM UTC-4, Stef wrote:
On 2020-10-23 Rick C wrote in comp.arch.fpga:

Someone said they had used an instantiated ADC in the Xilinx tools. Anyone know if that is actually an ADC or if it is an ADC chip interface?

On what Xilinx device? At least the Zynq devices do have actual ADC\'s.

Don\'t know yet. I\'m asking questions, but he specifically said instantiated \"IP\" but I suppose that might be the same as \"instantiating\" a clock block with PLL ect.

I\'m essentially interviewing him to work on this open source project and the real issue is how much he knows about delta-sigma converters and how to implement them.

Right now I\'d like to get an idea of whether it would significantly improve accuracy and/or noise to use separate comparator and driver for the analog interface. The sensors are powered from 5 volts and so produce a 5 volt analog output. The separate drivers and comparators could be powered from the same supply, separate from any other supply on the board for noise isolation. Also, as the sensor outputs are proportional to the power rail voltage, this will make all measurements ratiometric eliminating the need to correct for the power voltages. Otherwise we need to provide the I/O bank 3..3 volts that is a ratioed to the 5 volt rail. I guess no big deal. The point is it\'s not that much more to use separate comparators and drivers and may get us noise and accuracy advantages.

Sorry if this sounds irrelevant. I often uses newsgroup posts to solidify my thinking. In this case we have tons of I/Os available, so I think I\'m going to use both approaches and dedicate a bank of I/Os to the ADCs.

if you need to add external parts you might as well add a real adc

 

[Mike Perkins]

On 23/10/2020 19:07:53, Rick C wrote:

On Friday, October 23, 2020 at 3:02:53 AM UTC-4, Stef wrote:
On 2020-10-23 Rick C wrote in comp.arch.fpga:

Someone said they had used an instantiated ADC in the Xilinx
tools. Anyone know if that is actually an ADC or if it is an ADC
chip interface?

On what Xilinx device? At least the Zynq devices do have actual
ADC\'s.

Don\'t know yet. I\'m asking questions, but he specifically said
instantiated \"IP\" but I suppose that might be the same as
\"instantiating\" a clock block with PLL ect.

I\'m essentially interviewing him to work on this open source project
and the real issue is how much he knows about delta-sigma converters
and how to implement them.

Right now I\'d like to get an idea of whether it would significantly
improve accuracy and/or noise to use separate comparator and driver
for the analog interface. The sensors are powered from 5 volts and
so produce a 5 volt analog output. The separate drivers and
comparators could be powered from the same supply, separate from any
other supply on the board for noise isolation. Also, as the sensor
outputs are proportional to the power rail voltage, this will make
all measurements ratiometric eliminating the need to correct for the
power voltages. Otherwise we need to provide the I/O bank 3.3 volts
that is a ratioed to the 5 volt rail. I guess no big deal. The point
is it\'s not that much more to use separate comparators and drivers
and may get us noise and accuracy advantages.

Sorry if this sounds irrelevant. I often uses newsgroup posts to
solidify my thinking. In this case we have tons of I/Os available,
so I think I\'m going to use both approaches and dedicate a bank of
I/Os to the ADCs.

Nothing wrong with thinking out loud.

Like another poster has suggested, and unless there is a tight budget in
terms of space or money, it can be cost effective in terms of design
time (and cost) to simply fit a known ADC to the PCB that has a known
spec and reduce overall risk.

--
Mike Perkins
Video Solutions Ltd
www.videosolutions.ltd.uk

 

[Rick C]

On Friday, October 23, 2020 at 4:50:09 PM UTC-4, lasselangwad...@gmail.com wrote:

fredag den 23. oktober 2020 kl. 20.28.58 UTC+2 skrev Rick C:
On Friday, October 23, 2020 at 1:35:45 PM UTC-4, lasselangwad...@gmail.com wrote:
fredag den 23. oktober 2020 kl. 07.10.53 UTC+2 skrev Rick C:
On Thursday, September 3, 2020 at 7:39:18 PM UTC-4, lasselangwad...@gmail.com wrote:
tirsdag den 1. september 2020 kl. 00.29.02 UTC+2 skrev Rick C:
On Monday, August 31, 2020 at 5:43:54 PM UTC-4, lasselangwad...@gmail.com wrote:
mandag den 31. august 2020 kl. 02.57.21 UTC+2 skrev Rick C:
I have looked at ADCs in FPGAs but never built one. Obviously sigma delta is a good way to go as it can be done all digitally, or almost so. I\'m not completely clear on how to do it.

Lattice has a reference design using an LVDS receiver as a comparator. They use an RC filter on the output bit as the reference voltage for the input. I\'m having trouble relating this to the typical block diagram of the sigma delta converter. Is this circuit the same thing?


I\'d say it is a delta modulator not a delta-sigma modulator

Sorry, I\'m not clear on what distinction you are trying to make.. First, what is \"it\"?


the commonly used \"RC filter on the output bit used as reference voltage\" I\'d call a delta modulator

in a delta-sigma input minus output is integrated and the reference voltage fixed

Here is my thinking. Some people talk about digital noise being the source of noise limitations in this technique. The I/O bank on FPGAs are separate from the rest of the chip and each other. We have plenty of spare I/Os so we can dedicate a bank to ADC use. Then the I/Os for the ADC are not just less noisy, but also it can be provided by it\'s own supply with lower noise and better accuracy... or more like tracking the 5 volt rail that powers the sensors.

I\'ve been mulling the distinction between delta-sigma (or sigma-delta, I can never remember) and the delta modulator. A simple mod to the analog circuit should make it a delta-sigma.

Vref -----------------| Vin-
|
Vin ---RRR---o---o----| Vin+
| | |
R --- |
R --- |
R | |
| V |
| |
+--------| SD out

This should provide the integration and quantization to be sigma-delta, right?

yes with the voltage on Vin almost constant it should be an ok approximation,
how well it works in practice I don\'t know

Not sure what you mean about constant Vin. Vin is the signal being measured.

I meant Vin+ the comparator input


Of course it needs to be band limited, but a main point of delta-sigma is that band is at the Nyquist rate of the input samples, a much wider band than the output band.

I\'m also not sure why you refer to this as an approximation. The resistors are performing the difference of the input and the feedback. The cap is the integrator. I suppose it\'s not a perfect integrator. Is it essentially equivalent to the other input circuit with the signal input as Vref and an RC from the feedback output to the differential input? Our decimation factor will be on the order of 32kibi.


an ideal integrator would charge the cap with a current proportional to the Vin
for that to happen Vin+ would need to be constant, it isn\'t quite

But that is a minor issue, second order at least since the action of the feedback will keep Vin+ very close to Vref. The Vin signal has no more weight than the feedback output so worst case if the input pegs at some point the feedback output will also peg and Vcap remains the same.

I see Lattice actually shows both input arrangements in their design note only saying the one above uses an extra resistor and I guess the Vref. They do mention that using Vref sets the point of operation. I don\'t think the differential inputs on the FPGAs are intended to range up and down the voltage scale so fixing it is useful. I suppose some scaling error can be removed by setting Vref with a 50/50 duty cycle output onto a similar RC. We will have several ADC, so Vref can be shared between them.

For a while I was thinking a single slope ADC could be used. Then Vref would need to be either a linear ramp or if an RC is used a log compensation would be needed once digitized. This can give 15 bits of resolution at 1 kSPS, but by ramping from Vcc to ground more resolution can be obtained at the low end which is useful for some of the inputs. Don\'t know about ENOB though. It would factor in Vcc so be a ratiometric measurement which is what we need. It\'s much simpler than the delta-sigma approach for sure. We have to do calculations on the measurements including a zero offset so adding a scale factor to compensate for the RC inaccuracy is not a big deal (measuring a Vref periodically). One of the measurements requires a divide to account for absolute pressure, so once we have a divide it can be used for any of the calcs. I guess this would require good temperature compensation in the RC. Either in the circuitry or in the calculations. We\'ll have a temperature measurement on the board.

--

Rick C.

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[Rick C]

On Friday, October 23, 2020 at 5:00:38 PM UTC-4, lasselangwad...@gmail.com wrote:

fredag den 23. oktober 2020 kl. 20.07.58 UTC+2 skrev Rick C:
On Friday, October 23, 2020 at 3:02:53 AM UTC-4, Stef wrote:
On 2020-10-23 Rick C wrote in comp.arch.fpga:

Someone said they had used an instantiated ADC in the Xilinx tools. Anyone know if that is actually an ADC or if it is an ADC chip interface?

On what Xilinx device? At least the Zynq devices do have actual ADC\'s..

Don\'t know yet. I\'m asking questions, but he specifically said instantiated \"IP\" but I suppose that might be the same as \"instantiating\" a clock block with PLL ect.

I\'m essentially interviewing him to work on this open source project and the real issue is how much he knows about delta-sigma converters and how to implement them.

Right now I\'d like to get an idea of whether it would significantly improve accuracy and/or noise to use separate comparator and driver for the analog interface. The sensors are powered from 5 volts and so produce a 5 volt analog output. The separate drivers and comparators could be powered from the same supply, separate from any other supply on the board for noise isolation. Also, as the sensor outputs are proportional to the power rail voltage, this will make all measurements ratiometric eliminating the need to correct for the power voltages. Otherwise we need to provide the I/O bank 3.3 volts that is a ratioed to the 5 volt rail. I guess no big deal. The point is it\'s not that much more to use separate comparators and drivers and may get us noise and accuracy advantages.

Sorry if this sounds irrelevant. I often uses newsgroup posts to solidify my thinking. In this case we have tons of I/Os available, so I think I\'m going to use both approaches and dedicate a bank of I/Os to the ADCs.


if you need to add external parts you might as well add a real adc

Not all parts are the same. The ADCs that give more than 12 bits on multiple channels are in the $5 and up range. I can get comparators for a quarter and CMOS buffers for a dime. I\'m not sure the comparators are needed. The buffer might help though.

--

Rick C.

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[Rick C]

On Friday, October 23, 2020 at 9:00:37 PM UTC-4, Mike Perkins wrote:

On 23/10/2020 19:07:53, Rick C wrote:
On Friday, October 23, 2020 at 3:02:53 AM UTC-4, Stef wrote:
On 2020-10-23 Rick C wrote in comp.arch.fpga:

Someone said they had used an instantiated ADC in the Xilinx
tools. Anyone know if that is actually an ADC or if it is an ADC
chip interface?

On what Xilinx device? At least the Zynq devices do have actual
ADC\'s.

Don\'t know yet. I\'m asking questions, but he specifically said
instantiated \"IP\" but I suppose that might be the same as
\"instantiating\" a clock block with PLL ect.

I\'m essentially interviewing him to work on this open source project
and the real issue is how much he knows about delta-sigma converters
and how to implement them.

Right now I\'d like to get an idea of whether it would significantly
improve accuracy and/or noise to use separate comparator and driver
for the analog interface. The sensors are powered from 5 volts and
so produce a 5 volt analog output. The separate drivers and
comparators could be powered from the same supply, separate from any
other supply on the board for noise isolation. Also, as the sensor
outputs are proportional to the power rail voltage, this will make
all measurements ratiometric eliminating the need to correct for the
power voltages. Otherwise we need to provide the I/O bank 3.3 volts
that is a ratioed to the 5 volt rail. I guess no big deal. The point
is it\'s not that much more to use separate comparators and drivers
and may get us noise and accuracy advantages.

Sorry if this sounds irrelevant. I often uses newsgroup posts to
solidify my thinking. In this case we have tons of I/Os available,
so I think I\'m going to use both approaches and dedicate a bank of
I/Os to the ADCs.

Nothing wrong with thinking out loud.

Like another poster has suggested, and unless there is a tight budget in
terms of space or money, it can be cost effective in terms of design
time (and cost) to simply fit a known ADC to the PCB that has a known
spec and reduce overall risk.

There will be a socket on the board for an ADC chip. I\'m not going to risk a board spin just for this idea. Risk mitigation. But at $5 each significant money can be saved in production by using an integrated ADC in the FPGA.

We actually don\'t need more than 10 bits for anything other than one sensor that will spend most of it\'s time in the very low end of the range. If I can get 12 useful bits we are probably ok. Using a single slope converter with calibration by measuring a Vref I can probably get better resolution at the low end and still have good results with the simpler circuit.

I\'m not sure how much \"noise\" will be a problem. The absolute accuracy is limited by the sensors to a couple percent. But we need good resolution for the control loop and for the flow rate which we are integrating into a volume.

Sometimes I talk myself into this being a snap and other times I worry it won\'t work worth a damn.

The delta-sigma circuits can be designed so they can be built to work with a mid-scale Vref and then allow for a single slope configuration with a common slope circuit. I was planning on using something like the single slope converter with the slower signals anyway. I should probably design something so it can be tested without involving the sensors since it will be hard to manipulate them to get a particular output voltage.

Or I can convince the group we should use digital sensors. Lol! Not sure why we picked analog sensors. I\'m having trouble finding anyone who carries stock on a board mounted differential pressure sensor other than the one we are using. The gage pressure sensor is available with a digital output though. Only $10.

--

Rick C.

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[Michael Kellett]

On 24/10/2020 05:30, Rick C wrote:

On Friday, October 23, 2020 at 5:00:38 PM UTC-4, lasselangwad...@gmail.com wrote:
fredag den 23. oktober 2020 kl. 20.07.58 UTC+2 skrev Rick C:
On Friday, October 23, 2020 at 3:02:53 AM UTC-4, Stef wrote:
On 2020-10-23 Rick C wrote in comp.arch.fpga:

Someone said they had used an instantiated ADC in the Xilinx tools. Anyone know if that is actually an ADC or if it is an ADC chip interface?

On what Xilinx device? At least the Zynq devices do have actual ADC\'s.

Don\'t know yet. I\'m asking questions, but he specifically said instantiated \"IP\" but I suppose that might be the same as \"instantiating\" a clock block with PLL ect.

I\'m essentially interviewing him to work on this open source project and the real issue is how much he knows about delta-sigma converters and how to implement them.

Right now I\'d like to get an idea of whether it would significantly improve accuracy and/or noise to use separate comparator and driver for the analog interface. The sensors are powered from 5 volts and so produce a 5 volt analog output. The separate drivers and comparators could be powered from the same supply, separate from any other supply on the board for noise isolation. Also, as the sensor outputs are proportional to the power rail voltage, this will make all measurements ratiometric eliminating the need to correct for the power voltages. Otherwise we need to provide the I/O bank 3.3 volts that is a ratioed to the 5 volt rail. I guess no big deal. The point is it\'s not that much more to use separate comparators and drivers and may get us noise and accuracy advantages.

Sorry if this sounds irrelevant. I often uses newsgroup posts to solidify my thinking. In this case we have tons of I/Os available, so I think I\'m going to use both approaches and dedicate a bank of I/Os to the ADCs.


if you need to add external parts you might as well add a real adc

Not all parts are the same. The ADCs that give more than 12 bits on multiple channels are in the $5 and up range. I can get comparators for a quarter and CMOS buffers for a dime. I\'m not sure the comparators are needed. The buffer might help though.

You are a bit out on price, you can buy an 8 channel part from
Microchip at about $3 5k off, MCP3464 (16 bit, 8 single ended or 4
differential channels).
That way you get a fully sorted part with with built in PGA and you
won\'t be at the mercy of using unspecified performance of the FPGA.

It would save you endless heartache in approval and
certification/qualification time - I certainly wouldn\'t want to get
involved with the FMEA for the FPGA sigma-delta design.

There may well be cheaper parts than this.

MK