ADC selection

[Michael]

I am trying to find an ADC that meets following requirements:
Easy ones:
10+ bits
Analog bandwidth 400MHz+
Acquisition delay jitter 10ps or less

Difficult one:
It has to be able to accept "slow" clock (down to 100kHz).

I have not been able to find one.
Is using external S/H the only way around it?
Thanks a lot for a suggestion!
Michael

 

[Rene Tschaggelar]

Michael wrote:

I am trying to find an ADC that meets following requirements:
Easy ones:
10+ bits
Analog bandwidth 400MHz+
Acquisition delay jitter 10ps or less

Difficult one:
It has to be able to accept "slow" clock (down to 100kHz).

I have not been able to find one.
Is using external S/H the only way around it?

You won't get a 10ps jitter from a 100kHz clock.

Rene
--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net

 

[John Larkin]

On Thu, 13 May 2004 15:53:48 +0200, Rene Tschaggelar <none@none.net>
wrote:

You won't get a 10ps jitter from a 100kHz clock.

Why not? Dividing down a decent, say, 20 MHz TCXO should give
single-digit ps jitter at 100K, or even 10K. I have one product that
manages about 3 ps jitter at 960 Hz, just dividing a 155 MHz
oscillator.

John

 

[John Larkin]

On 13 May 2004 04:27:24 -0700, mkogan02492@yahoo.com (Michael) wrote:

I am trying to find an ADC that meets following requirements:
Easy ones:
10+ bits
Analog bandwidth 400MHz+
Acquisition delay jitter 10ps or less

Difficult one:
It has to be able to accept "slow" clock (down to 100kHz).

I have not been able to find one.
Is using external S/H the only way around it?
Thanks a lot for a suggestion!
Michael

Pipeline ADCs don't like to go slow. Can you clock at a higher rate
and throw away the samples you don't want? The only good s/h circuits
around are buried inside the ADCs!

What's it for?

John

 

[Ben Bradley]

On 13 May 2004 04:27:24 -0700, mkogan02492@yahoo.com (Michael) wrote:

I am trying to find an ADC that meets following requirements:
Easy ones:
10+ bits
Analog bandwidth 400MHz+
Acquisition delay jitter 10ps or less

Difficult one:
It has to be able to accept "slow" clock (down to 100kHz).
I have not been able to find one.
Is using external S/H the only way around it?

No. Sample at the ADC's "regular" high frequency clock speed and
add a counter and glue logic so whatever it's connected to sees "data
ready" on only one out of 1,000 (or howevermany is appropriate)
samples.

Thanks a lot for a suggestion!
Michael

-----
http://mindspring.com/~benbradley

 

[Rene Tschaggelar]

John Larkin wrote:

On Thu, 13 May 2004 15:53:48 +0200, Rene Tschaggelar <none@none.net
wrote:


You won't get a 10ps jitter from a 100kHz clock.


Why not? Dividing down a decent, say, 20 MHz TCXO should give
single-digit ps jitter at 100K, or even 10K. I have one product that
manages about 3 ps jitter at 960 Hz, just dividing a 155 MHz
oscillator.

I was under the impression they wanted to PLL it up to the
400MHz. No ?

Rene

 

[John Larkin]

On Thu, 13 May 2004 18:14:14 +0200, Rene Tschaggelar <none@none.net>
wrote:

John Larkin wrote:

On Thu, 13 May 2004 15:53:48 +0200, Rene Tschaggelar <none@none.net
wrote:


You won't get a 10ps jitter from a 100kHz clock.


Why not? Dividing down a decent, say, 20 MHz TCXO should give
single-digit ps jitter at 100K, or even 10K. I have one product that
manages about 3 ps jitter at 960 Hz, just dividing a 155 MHz
oscillator.

I was under the impression they wanted to PLL it up to the
400MHz. No ?

Rene

He needs an ADC with 400 MHz analog (ie, s/h) bandwidth, but he
doesn't want to sample that fast. Pipelined ADCS are available with
this sort of bw, that can be clocked down to something like the 10 MHz
range. We don't know what his prime clock frequency is... it may be
100K, or it may be higher.

One *could* lock a 10 MHz crystal oscillator to a 100K source and keep
the jitter down below 10 ps, with a fairly narrowband loop. But - as
usual - we don't know the details.

John