Actual for formal is not a signal

[Olaf]

Hi,

there are some problems accumulated on this weekend, sorry

Well, I have to following peace of code:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity stage is

port(
...
set_config : in std_ulogic;
data : in std_ulogic_vector(31 downto 0);
...
end entity;
-------------------------------------------------------------------------------
architecture behavioral of trigger_stage is

signal rg_timer : std_ulogic_vector(15 downto 0);
signal rg_level : std_ulogic_vector(7 downto 0);
signal rg_combine : std_ulogic_vector(1 downto 0);
...
begin
-- vcom complains if a signal is missing
configure: process (conf_clk, reset, set_config, set_bit_mask,
set_bit_value, set_edge_mask, set_fe_mask,
set_re_mask, data)
is

-------------------------------------------------------------------------
variable set : std_ulogic_vector(5 downto 0);
variable n : positive;

-------------------------------------------------------------------------
function to_onehot (signal level : natural)
return std_ulogic_vector
is
variable tmp : unsigned(8 downto 0)
:= (0 => '1', others => '0');
begin
tmp := tmp sll level;
return std_ulogic_vector(tmp(8 downto 1));
end function;
------------------------------------------------------
begin
set := set_bit_value &
set_bit_mask &
set_re_mask &
set_fe_mask &
set_edge_mask &
set_config;
if (reset = RESET_ACTIVE) then
...
elsif rising_edge(conf_clk) then
case set is
...
when b"000001" =>
rg_timer <= data(31 downto 16);
n := to_integer(unsigned(data(7 downto 4)));
rg_level <= to_onehot; -- ERROR
rg_combine <= data(1 downto 0);
when others => null;
end case;
end if;
end process;
...

The goal is to demux an integer bitfield data(7 downto 4) into a
"one-hot" sulv. I've got the error:

Actual (variable "n") for formal "level" is not a signal.

Do I have really to introduce an extra signal or is there another way?

The goal is to compare the register rg_level with a "counter" value of
an other process, which shifts the '1' on rising edge pending on some
other hit conditions. On compare match further actions are performed.

Thanks
Olaf

 

[Mike Treseler]

Olaf wrote:

-- vcom complains if a signal is missing
configure: process (conf_clk, reset, set_config, set_bit_mask,
set_bit_value, set_edge_mask, set_fe_mask,
set_re_mask, data)

Ignore the warning
do this instead:

configure: process (conf_clk, reset)

begin
set := set_bit_value &
set_bit_mask &
set_re_mask &
set_fe_mask &
set_edge_mask &
set_config;

put "set := ..." below the "elsif"

Be sure to initialize all of the variables
in the if clause.

The goal is to demux an integer bitfield data(7 downto 4) into a
"one-hot" sulv. I've got the error:

Actual (variable "n") for formal "level" is not a signal.

use a default function parameter:

function to_onehot (level : natural)
return std_ulogic_vector

-- Mike Treseler

 

[Olaf]

Thanks Mike,

Actual (variable "n") for formal "level" is not a signal.

use a default function parameter:

function to_onehot (level : natural)
return std_ulogic_vector

writing the function more generic:

function to_onehot (level : std_ulogic_vector)
return std_ulogic_vector
is
constant L : integer := level'high;
constant R : integer := level'low;
variable n : positive := to_integer(unsigned(level));
variable tmp : unsigned(L+1 downto 0) := (0 => '1', others =>
'0'); -- ERROR
begin
tmp := tmp sll n;
return std_ulogic_vector(tmp(L+1 downto R+1));
end function;


got:

vcom -quiet -check_synthesis -work work ...
Non-locally static OTHERS choice is allowed only if it is the only
choice of the only association.

Attributes are not easy ... A assume, the problem is related to 0 =>
'1': setting the lsb to '1' which is shifted later.

Thanks
Olaf

 

[Mike Treseler]

Olaf wrote:

Thanks Mike,
got:

vcom -quiet -check_synthesis -work work ...
Non-locally static OTHERS choice is allowed only if it is the only
choice of the only association.

hmm. If the number of states is n,
the onehot vector length is 2**(n-1)
Your function needs a subtype declaration for the output vector.

-- Mike Treseler

 

[Mike Treseler]

Mike Treseler wrote:

If the number of states is n,
If the "number of states" vector *has length* n, then

the onehot vector length is 2**(n-1)

-- Mike Treseler